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ALPS: an algorithm for pipeline data path synthesis
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Source International Symposium on Microarchitecture archive
Proceedings of the 24th annual international symposium on Microarchitecture table of contents
Albuquerque, New Mexico, Puerto Rico
Pages: 124 - 132  
Year of Publication: 1991
ISBN:0-89791-460-0
Authors
Ramesh Karri  Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA
Alex Orailoğlu  Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
ACM  New York, NY, USA
Bibliometrics
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
P. B. Denyer , David Renshaw, VLSI Signal Processing; A Bit-Serial Approach, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985
 
2
S. Devadas and A. R. Newton. Algorithms for hardware allocation in data path synthesis. IEEE transactions on CAD, 8(7):768-781, 1989.
 
3
E. Girczyc. Loop Winding- A data flow approach to function M pipelining. In Proceedings of the IEEE Internatzonal Symposium of Circuits and Systems, pages 382-385, May 1987.
4
Cheng-Tsung Hwang , Yu-Chin Hsu , Youn-Long Lin, Scheduling for functional pipelining and loop winding, Proceedings of the 28th conference on ACM/IEEE design automation, p.764-769, June 17-22, 1991, San Francisco, California, United States  [doi>10.1145/127601.127766]
 
5
K. S. Hwang, A. E. Casavant, C. T. Chang, and M. A. d'Abreu. Scheduling and Hardware sh~ring in pipelined data paths. In Proceedings o/the {CCAD, pages 24-27, 1989.
 
6
P. M. Kogge. The architecture of pipelined computers. McGraw-Hill, 1981.
 
7
N. Park and A. C. Parker. A software package for synthesis of pipelines from behavioral specifications. IEEE transactions on CAD, 7(3):356-370, 1988.
 
8
P.G. Paulin and J. P. Knight. Force-directed scheduling for the behavioral synthesis of ASICs. IEEE transactions on CAD, 8(6):661-679, 1989.
9
Roni Potasman , Joseph Lis , Alexandru Nicolau , Daniel Gajski, Percolation based synthesis, Proceedings of the 27th ACM/IEEE conference on Design automation, p.444-449, June 24-27, 1990, Orlando, Florida, United States  [doi>10.1145/123186.123333]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Data-path design

  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Sequencing and scheduling


Keywords:
functional pipelining, high-level synthesis

Collaborative Colleagues:
Ramesh Karri: colleagues
Alex Orailoğlu: colleagues

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