Implementation optimization techniques for architecture synthesis of application-specific processors

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Implementation optimization techniques for architecture synthesis of application-specific processors

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International Symposium on Microarchitecture archive
Proceedings of the 24th annual international symposium on Microarchitecture table of contents

Albuquerque, New Mexico, Puerto Rico

Pages: 114 - 123

Year of Publication: 1991

ISBN:0-89791-460-0

Authors

Mauricio Breternitz, Jr.	Advanced Workstations Division, IBM-Austin, TX
John Paul Shen	ECE Department, Carnegie-Mellon University

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 3, Citation Count: 0

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references index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
	2	M. Breternitz and A. Nicolau. Tradeoffs between pipelining and multiple functional units in finegrain parallelism exploitation. ICS-90 International Conference on $upercomputing, Santa Clara CA, April 1989.
	3	Mauricio Breternitz, Jr. , John Paul Shen, Architecture synthesis of high-performance application-specific processors, Proceedings of the 27th ACM/IEEE conference on Design automation, p.542-548, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123398]
	4	Raul Compasano , Reinaldo A. Bergamaschi, Synthesis using path-based scheduling: algorithms and exercises, Proceedings of the 27th ACM/IEEE conference on Design automation, p.450-455, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123335]
	5	G. J. Chaitin, Register allocation & spilling via graph coloring, Proceedings of the 1982 SIGPLAN symposium on Compiler construction, p.98-105, June 23-25, 1982, Boston, Massachusetts, United States
	6	V. Chvátal , N. Sbihi, Recognizing claw-free perfect graphs, Journal of Combinatorial Theory Series A, v.44 n.3, p.154-176, April 1987
	7	1{. Cole and J. Hopcroft. On edge coloring bipartite graphs. SIAM Tr. Comp., Aug 1982.
	8	K. Ebcio~lu. Some design ideas for a VLIW architecture for sequential-natured software. Proceeding of the IFIP Working Conference o~ Parallel Processing, April 1988.
	9	K. Ebcioğlu , Toshio Nakatani, A new compilation technique for parallelizing loops with unpredictable branches on a VLIW architecture, Selected papers of the second workshop on Languages and compilers for parallel computing, p.213-229, May 1990, Urbana, Illinois, United States
	10	Joseph A. Fisher, Very Long Instruction Word architectures and the ELI-512, Proceedings of the 10th annual international symposium on Computer architecture, p.140-150, June 13-17, 1983, Stockholm, Sweden
	11	B. S. Haroun and M. I. Elmasry. Automatic synthesis of a multi-bus architecture for DSP. ICCAD, Nov 1988.
	12	W. L. Hsu and G. L. Nemhauser. Algorithms for maximum weight cliques, minimum weighted clique covers and minimum colorings of claw-free perfect graphs. Annals of Discrete Mathematics ~1, 1984.
	13	Mauricio Breternitz, Jr., Architecture synthesis of high-performance application-specific processors, University of Massachusetts, Amherst, MA, 1991
	14	ed. L. W. Beineke, R. J. Wilson. Selected Topics in Graph Theory. Academic Press, 1978.
	15	Alexandru Nicolau, Percolation Scheduling: A Parallel Compilation Technique, Cornell University, Ithaca, NY, 1985
	16	A. Wolfe , M. Breternitz, Jr. , C. Stephens , A. L. Ting , D. B. Kirk , R. P. Bianchini, Jr. , J. P. Shen, The white dwarf: a high-performance application-specific processor, Proceedings of the 15th Annual International Symposium on Computer architecture, p.212-222, May 30-June 02, 1988, Honolulu, Hawaii, United States
	17	Y.Neuvo, D.Chengyu, and S.K.Mitra. Interpolated finite impulse response filters. IEEE Trans. ASSP, June 1984.

INDEX TERMS

Primary Classification:
D. Software
D.3 PROGRAMMING LANGUAGES
D.3.4 Processors
Subjects: Optimization

Additional Classification:
C. Computer Systems Organization
C.4 PERFORMANCE OF SYSTEMS
Subjects: Performance attributes

General Terms:
Algorithms, Measurement, Performance, Theory

Collaborative Colleagues:

Mauricio Breternitz, Jr.: colleagues

John Paul Shen: colleagues

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