The combination of scheduling, allocation, and mapping in a single algorithm

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The combination of scheduling, allocation, and mapping in a single algorithm

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE Design Automation Conference table of contents

Orlando, Florida, United States

Pages: 71 - 76

Year of Publication: 1991

ISBN:0-89791-363-9

Authors

Richard J. Cloutier	Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Donald E. Thomas	Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 22, Citation Count: 22

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ABSTRACT

We present a single high level synthesis algorithm that schedules the operations of a data dependence graph, allocates the necessary hardware, and maps the operations to specific functional units. This is achieved by extending the global analysis approach developed for force-directed scheduling to include individual module instances. This new algorithm should be applicable to any behavioral synthesis system that schedules operations from a data dependence graph.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Donald E. Thomas , Elizabeth D. Lagnese , John A. Nestor , Jayanth V. Rajan , Robert L. Blackburn , Robert A. Walker, Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench, Kluwer Academic Publishers, Norwell, MA, 1989
	2	E. F. Girczyc, Automatic Generation of Microsequenced Data Paths to Realize Ada Circuit Descriptions. PhD thesis, Carleton University, Ottawa, Canada, July 1984.
	3	M. Balakrishnan, "RT-Level Synthesis Based On Integrated Scheduling and Binding," Tech. Report 8813, Institute for Informatik der Universi~t Kiel, De~emk~r 1988.
	4	S. Devadas and A. R. Newton, "Algorithms for Hardware Allocation in Data Path Synthesis," IEEE Transactions On Computer-Aided Design Of Integrated Circuits, vol. 8, pp. 768-781, July 1989.
	5	P. G. Paulin and J. P. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASIC's,'" IEEE Transactions on Computer-Aided Design of Integrated Circuita, vol. 8, pp. 661-679, June 1989.
	6	S. Y. Kung , Thomas Kailath , Harper J. Whitehouse, VLSI and Modern Signal Processing, Prentice Hall Professional Technical Reference, 1984

CITED BY 22

	Richard J. Cloutier , Donald E. Thomas, Synthesis of pipelined instruction set processors, Proceedings of the 30th international conference on Design automation, p.583-588, June 14-18, 1993, Dallas, Texas, United States
	M. Rim , R. Jain , R. De Leone, Optimal allocation and binding in high-level synthesis, Proceedings of the 29th ACM/IEEE conference on Design automation, p.120-123, June 08-12, 1992, Anaheim, California, United States
	R. Moreno , R. Hermida , M. Fernández, Register estimation in unscheduled dataflow graphs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.3, p.396-403, July 1996
	Lawrence F. Arnstein , Don Thomas, A general consistency technique for increasing the controllability of high level synthesis tools, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.741-744, November 07-11, 1993, Santa Clara, California, United States
	W. F. J. Verhaegh , P. E. R. Lippens , E. H. L. Aarts , J. H. M. Korst , A. van der Werf , J. L. van Meerbergen, Efficiency improvements for force-directed scheduling, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.286-291, November 1992, Santa Clara, California, United States
	Rajiv Jain , Ashutosh Mujumdar , Alok Sharma , Hueymin Wang, Empirical evaluation of some high-level synthesis scheduling heuristics, Proceedings of the 28th conference on ACM/IEEE design automation, p.686-689, June 17-22, 1991, San Francisco, California, United States
	R. Dutta , J. Roy , R. Vemuri, Distributed design-space exploration for high-level synthesis systems, Proceedings of the 29th ACM/IEEE conference on Design automation, p.644-650, June 08-12, 1992, Anaheim, California, United States
	Herman Schmit , Donald E. Thomas, Array mapping in behavioral synthesis, Proceedings of the 8th international symposium on System synthesis, p.90-95, September 13-15, 1995, Cannes, France
	Vasily G. Moshnyaga , Hiroshi Mori , Hidetoshi Onodera , Keikichi Tamaru, Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.100-103, November 07-11, 1993, Santa Clara, California, United States
	Wenrui Gong , Gang Wang , R. Kastner, Storage assignment during high-level synthesis for configurable architectures, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.3-6, November 06-10, 2005, San Jose, CA
	Lawrence F. Arnstein , Don Thomas, Applications of attributed-behavior synthesis, Proceedings of the 7th international symposium on High-level synthesis, p.29-34, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
	William E. Dougherty , Donald E. Thomas, Unifying behavioral synthesis and physical design, Proceedings of the 37th conference on Design automation, p.756-761, June 05-09, 2000, Los Angeles, California, United States
	Ankur Srivastava , Seda Ogrenci Memik , Bo-Kyung Choi , Majid Sarrafzadeh, Achieving Design Closure Through Delay Relaxation Parameter, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.54, November 09-13, 2003
	Forrest Brewer , Barry Pangrle , Andrew Seawright, Interconnection synthesis with geometric constraints, Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture, p.158-165, November 27-29, 1990, Orlando, Florida, United States
	Soheil Ghiasi , Elaheh Bozorgzadeh , Karlene Nguyen , Majid Sarrafzadeh, Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System, Journal of VLSI Signal Processing Systems, v.42 n.1, p.43-55, January 2006
	Barry M. Pangrle , Forrest D. Brewer , Donald A. Lobo , Andrew Seawright, Relevant issues in high-level connectivity synthesis, Proceedings of the 28th conference on ACM/IEEE design automation, p.607-610, June 17-22, 1991, San Francisco, California, United States
	Seda Ogrenci Memik , Ryan Kastner , Elaheh Bozorgzadeh , Majid Sarrafzadeh, A scheduling algorithm for optimization and early planning in high-level synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.33-57, January 2005
	Reinaldo A. Bergamaschi , Raul Camposano , Michael Payer, Data-path synthesis using path analysis, Proceedings of the 28th conference on ACM/IEEE design automation, p.591-596, June 17-22, 1991, San Francisco, California, United States
	M. Nourani , C. Papachristou, Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems, Proceedings of the 29th ACM/IEEE conference on Design automation, p.99-105, June 08-12, 1992, Anaheim, California, United States
	Lawrence F. Arnstein , Don Thomas, The attributed-behavior abstraction and synthesis tools, Proceedings of the 31st annual conference on Design automation, p.557-561, June 06-10, 1994, San Diego, California, United States
	B. Gregory , D. MacMillen , D. Fogg, ISIS: a system for performance driven resource sharing, Proceedings of the 29th ACM/IEEE conference on Design automation, p.285-290, June 08-12, 1992, Anaheim, California, United States
	Jayanta Roy , Nand Kumar , Rajiv Dutta , Ranga Vemuri, DSS: A Distributed High-Level Synthesis System, IEEE Design & Test, v.9 n.2, p.18-32, April 1992