Skew spreading for peak current reduction

ABSTRACT

This paper presents a circuit optimization technique called skewspreading. Given an edge-triggered sequential circuit, skew spreadingderives the required clock arrival times for all registers so that theskews are distributed evenly in a preselected time window without changing the operating frequency of the circuit. Skew spreading is ideal for peak current reduction, since it distributes clock activities and the ensuing signal activities widely in time. We have developed a skew spreading algorithm and applied it to a suite of benchmark circuits. Simulation results demonstrate that the variance of the resulting skew from the uniform distribution can be reduced to 4% on the average. In comparison to other gate-level peak current reduction techniques, our scheme achieves an average improvement of 17% with a speedup of up to 13.9 times.

REFERENCES

• 1: R. B. Deokar and S. S. Sapatnekar. A graph-theoretic approach to clock skew optimization. In Proc. Inter. Symp. on Circuits and Systems, pages 407--410, May 1994.
• 2: John P. Fishburn, Clock Skew Optimization, IEEE Transactions on Computers, v.39 n.7, p.945-951, July 1990 [doi>10.1109/12.55696]
• 3: Ivan S. Kourtev , Eby G. Friedman, Clock skew scheduling for improved reliability via quadratic programming, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.239-243, November 07-11, 1999, San Jose, California, United States
• 4: Wai-Ching Douglas Lam , Cheng-Kok Koh , Chung-Wen Albert Tsao, Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy, Proceedings of the 4th International Symposium on Quality Electronic Design, p.327, March 24-26, 2003
• 5: A. Mukherjee and R. Sankaranarayan. Retiming and clock scheduling to minimize simultaneous switching. In IEEE SOC Conference, Sept. 2004.
• 6: José Luis Neves , Eby G. Friedman, Optimal clock skew scheduling tolerant to process variations, Proceedings of the 33rd annual conference on Design automation, p.623-628, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240636]
• 7: P. Vuillod , L. Benini , A. Bogliolo , G. De Micheli, Clock skew optimization for peak current reduction, Proceedings of the 1996 international symposium on Low power electronics and design, p.265-270, August 12-14, 1996, Monterey, California, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Optimization

General Terms:
Algorithms

Keywords:
clock scheduling, clock skew, low power