An asynchronous fpga logic cell implementation

ABSTRACT

We present a new method for implementing asynchronous FPGA logic cells which are configurable at pipeline level. Previous implementations of the basic elements of these logic cells were based on the pre-charged logic implementation which imposes some limitations on the size of the logic cell due to the stacking problem. To overcome this limitation we propose a novel method for implementing these templates. Our method uses standard single-rail computational circuits. It does not have any stacking problem and is not limited in size. The results show that a 4-input logic cell implemented by this method outperforms a previous 3-input logic cell by 16% in speed and 29% in power with a negligible area overhead.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

General Terms:
Design, Experimentation, Performance

Keywords:
FPGA, PCHB, a synchronous design, logic cell