Decomposition of instruction decoders for low-power designs

ABSTRACT

During the execution of processor instruction, decoding the instructions is a major task in identifying instructions and generating control signals for data paths. In this article, we propose two instruction decoder decomposition techniques for low-power designs. First, by tracing program execution sequences, we propose an algorithm that explores the relations between frequently executed instructions. Second, we propose a two-stage low-power decomposition structure for decoding instructions. Experimental results demonstrate that our proposed techniques achieve an average of 34.18% in power reduction and 12.93% in critical-path delay reduction for the instruction decoder.

REFERENCES

• 1: ARM Ltd. 1995. An introduction to thumb.
• 2: Sue-Hong Chow , Yi-Cheng Ho , TingTing Hwang , C. L. Liu, Low power realization of finite state machines—a decomposition approach, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.3, p.315-340, July 1996 [doi>10.1145/234860.234862]
• 3: Goldenberg, C., Baron, N., and Rosenshein Z. 1996. Small-Area, low-power instruction decoder. Tech. Rep. Motorola.
• 4: John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996
• 5: Bruce K. Holmer , Barton Sano , Michael Carlton , Peter Van Roy , Ralph Haygood , William R. Bush , Alvin M. Despain , Joan M. Pendleton , Tep Dobry, Fast Prolog with an extended general purpose architecture, Proceedings of the 17th annual international symposium on Computer Architecture, p.282-291, May 28-31, 1990, Seattle, Washington, United States
• 6: Intel. 1995. PentiumgPro Family Developer's Manual, vol. 2: Programmer's Reference Manual, Intel Corp., Santa Clara, CA.
• 7: Kissell, D. K. 1997. MIPS16: High density MIPS for the embedded market. Tech. Rep., Silicon Graphics MIPS group.
• 8: Wu-An Kuo , TingTing Hwang , Allen C. -H. Wu, Decomposition of Instruction Decoder for Low Power Design, Proceedings of the conference on Design, automation and test in Europe, p.10664, February 16-20, 2004
• 9: Lin, B. and Newton, A. R. 1989. Synthesis of multiple level logic from symbolic high-level description languages. In Proceedings of the International Conference on Very Large Scale Integration. 187--196.
• 10: W. Tang , R. Gupta , A. Nicolau, Power Savings in Embedded Processors through Decode Filer Cache, Proceedings of the conference on Design, automation and test in Europe, p.443, March 04-08, 2002

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Control design

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.1 Single Data Stream Architectures

General Terms:
Design

Keywords:
Low power, instruction decoder