Using a software testing technique to identify registers for partial scan implementation

ABSTRACT

Scan design has been widely used to ease test generation process for digital circuits. Although full scan approach results in high fault coverage while reducing ATPG effort, it introduces area and performance overheads that are most times unacceptable. Hence, partial scan is a commonly used technique to improve testability of sequential circuits while respecting design constraints. In this paper, we present a method to select sequential elements (flip-flops) to compose a partial scan chain. We use a software engineering technique to identify internal variables or signals of the circuit's behavioral description that have low observability. Experiments demonstrate that our approach achieves a high fault coverage including few flip-flops in the scan chain. Moreover, comparative results show that, for complex circuits, proposed technique is more efficient than some classical methods in selecting flip-flops to compose partial scan.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Design, Experimentation, Measurement, Reliability

Keywords:
automatic test generation, hardware description language, hardware testing, partial scan design, testability improvement