Power constrained design optimization of analog circuits based on physical gm/ID characteristics

ABSTRACT

This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/I_D characteristics as a design optimization guide. Our custom layout tool LIT implements and uses the ACM MOS compact model in the optimization loop. The methodology is implemented for automation within LIT and exploits all design space through the simulated annealing optimization process, providing solutions close to optimum with a single technology-dependent curve and accurate expressions for transconductance and current valid in all operation regions. The compact model itself contributes to convergence and to optimized implementations, since it has analytic expressions which are continuous in all current regimes, including weak and moderate inversion. The advantage of constraining the optimization within a power budget is of great importance for low-power CMOS. As examples we show the optimization results obtained with LIT, resulting in significant power savings, for the design of a two-stage Miller operational amplifier.

REFERENCES

• 1: P. E. Allen and D. R. Holberg. CMOS Analog Circuit Design. Oxford University Press, Oxford, second edition, 2002.
• 2: R. M. Coitinho, L. H. Spiller, M. C. Schneider, and C. Galup-Montoro. A simplified methodology for the extraction of acm most model parameters. In 14th Symposium on Integrated Circuits and Systems Design, pages 136--141, Brasília, Brazil, September 2001.
• 3: A. I. A. Cunha, M. C. Schneider, and C. Galup-Montoro. An MOS transistor model for analog circuit design. IEEE Journal of Solid-State Circuits, 33(10):1510--1519, October 1998.
• 4: B. de Smedt and G. G. E. Gielen. Watson: Design space boundary exploration and model generation for analog and rf ic design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(2):213--224, Feb 2003.
• 5: M. Degrauwe, O. Nys, E. Dukstra, J. Rijmenants, S. Bitz, B. L. A. G. Goffart, E. A. Vittoz, S. Cserveny, C. Meixenberger, G. V. der Stappen, and H. J. Oguey. IDAC: An interactive design tool for analog CMOS circuits. IEEE Journal of Solid-State Circuits, SC-22(6):1106--1116, December 1987.
• 6: F. El-Turky and E. E. Perry. BLADES: An artificial intelligence approach to analog circuit design. IEEE Transactions on Computer-Aided Design, 8(6):680--692, June 1989.
• 7: G. E. Gielen, H. C. C. Walscharts, and W. M. C. Sansen. Analog circuit design optimization based on symbolic simulation and simulated annealing. IEEE Journal of Solid-State Circ., 25(3):707--713, June 1990.
• 8: G. G. E. Gielen, H. C. C. Walscharts, and W. M. C. Sansen. ISAAC: A symbolic simulator for analog integrated circuits. IEEE Journal of Solid-State Circuits, 24(6):1587--1597, December 1989.
• 9: A. Girardi and S. Bampi. Lit - an automatic layout generation tool for trapezoidal association of transistors for basic analog building blocks. In Proceedings of the Design Automation and Test in Europe, March 2003.
• 10: R. Harjani, R. A. Rutenbar, and L. R. Carley. OASYS: A framework for analog circuit synthesis. IEEE Transactions on Computer Aided Design, 8(12), 1989.
• 11: M. D. M. Hershenson, S. P. Boyd, and T. H. Lee. Optimal design of a CMOS op-amp via geometric programming. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 20(1):1--21, January 2001.
• 12: S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by simulated annealing. Science, 220(4598):671--680, May 1983.
• 13: F. Silveira, D. Flandre, and P. G. A. Jespers. A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA. IEEE Journal of Solid-State Circuits, 31(9):1314--1319, September 1996.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Design, Performance, Reliability

Keywords:
analog design, simulated annealing, synthesis