A test chip for automatic MOSFET mismatch characterization

ABSTRACT

This paper describes a test circuit for intensive characterization of MOS transistors mismatch. It aggregates analog switches, a shift register and a reference circuit, as well as the matrix of 1296 transistors to be tested. This circuit was integrated in a 0.35 mm bulk technology, and was designed to give experimental support for our MOSFET mismatch model. The test chip was characterized over a wide range of operation conditions, from weak to strong inversion, from linear to saturation region, allowing the analysis of MOSFET mismatch from bias, process and geometric parameters.

REFERENCES

• 1: J-B Shyu, G. C. Temes, and F. Krummenacher, "Random error effects in matched MOS capacitors and current sources", IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 948--955, Dec. 1984.
• 2: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors", IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433--1440, Oct. 1989.
• 3: J. Pineda-Gyvez and H. P. Tuinhout "Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits", IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 157--168, Jan. 2004.
• 4: H. Klimach, C. Galup-Montoro, M.C. Schneider, and A. Arnaud, "MOSFET Mismatch Modeling: A New Approach", IEEE Design & Test of Computers, vol. 23, no. 1, pp 20--29, Jan. 2006.
• 5: H. Klimach, A. Arnaud, M.C. Schneider, and C. Galup-Montoro, "Characterization of MOS transistor current mismatch", Proc. 17th Symposium on Integrated Circuits and Systems Design, SBCCI 2004, pp. 33--38, 2004.
• 6: C. Galup-Montoro, M.C. Schneider, H. Klimach, and A. Arnaud, "A compact model of MOSFET mismatch for circuit design", IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1649--1657, Aug. 2005.
• 7: A. Pergoot, B. Graindourze, E. Janssens et al. "Statistics for matching", Proc. 1995 International Conference on Microelectronic Test Structures, pp. 193--197, March 1995.
• 8: M. Quarantelli et al., "Characterization and modeling of MOSFET mismatch of a deep submicron technology", Proc. IEEE 2003 Int. Conference on Microelectronic Test Structures, pp. 238--243, 2003.
• 9: H. P. Tuinhout, "Design of matching test structures", Proc. IEEE 1994 Int. Conference on Microelectronic Test Structures, pp. 21--27, 1994.
• 10: M-F. Lan and R. Geiger, "Impact of model errors on predicting performance of matching-critical circuits, Proc. 43rd. IEEE Midwest Symp. on Circuits and Systems, pp.1324--1328, 2000.
• 11: H. Yang et al. "Current mismatch due to local dopant fluctuations in MOSFET channel", IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2248--2254, Nov. 2003.
• 12: F. Forti and M. E. Wright, "Measurements of MOS current mismatch in the weak inversion region", IEEE J. Solid-State Circuits, vol. 29, no. 2, pp. 138--142, Feb. 1994.
• 13: A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro, "An MOS transistor model for analog circuit design", IEEE J. Solid-State Circuits, vol.33, no.10, pp. 1510--1519, Oct.1998.
• 14: T. Mizuno, "Influence of statistical spacial-nonunifirmity of dopant atoms on threshold voltage in a system of many MOSFETs", Jpn. J. Appl. Phys., vol. 35, pp. 842--848, 1996.
• 15: S. J. Lovett et al., "Sensitivity of MOS transistor mismatch to device dimensions and suggestions on how to improve matching performance", Proc. IEEE 1995 Colloquium on Improving the Efficiency of IC Manufacturing Technology, pp. 11/1--11/5, 1995.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Experimentation, Measurement, Performance

Keywords:
MOSFET, analog design, characterization, matching, mismatch