Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration

ABSTRACT

High parallelism degree is fundamental for high speed image processing systems. Modern FPGA devices can provide such parallelism plus flexibility. Temporal partitioning techniques can be used to implement large systems, splitting them into partitions (called contexts), multiplexed in a FPGA. This approach can increase the effective FPGA area, allowing high parallelism in the application tasks. However, the context reconfigurations can cause performance decrease. Intensive parallelism exploration of massive image data application compensates this overhead and can improve global performance. In this work, one reconfigurable computer platform and design space exploration techniques are proposed for mapping of image processing applications into FPGA slices. A library with different hardware implementation for different parallelism degree is used to better adjust space/time for each task. Experiments demonstrate the efficiency of the approach when compared to the optimal mapping reached by exhaustive timing search in the complete design space exploration.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Automatic synthesis

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Optimization

General Terms:
Algorithms, Design, Experimentation, Performance

Keywords:
FPGA-computers, area-time trade-offs, design space exploration, image processing, temporal partitioning techniques