FPGA architecture for static background subtraction in real time

ABSTRACT

Background subtraction is a method typically used to segment moving regions in image sequences taken from a static camera by comparing each new frame to a model of the scene background. In this paper, we present an FPGA architecture for background subtraction, taking advantage of the data and logical parallel opportunities offered by a field programmable gate array (FPGA) architecture. At a clock rate of 40 MHz, the architecture can process 30 frames per second, where the image resolution is 240 x 120. The capability of the system is demonstrated for several tests and video sequences.

REFERENCES

• 1: T. Alexandropoulos, V. Loumos, and E. Kayafas, Eleftherios. A block-based clustering technique for real-time object detection on a static background. In 2nd International IEEE Conference on Intelligent Systems, Varna, Bulgaria, June 22-24, 2004.
• 2: T. Horprasert, D. Harwood, and L. S. Davis. A Statistical Approach for Real Time Robust Background Subtraction. In IEEE ICCV'99 FRAME-RATE WORKSHOP, 1999.
• 3: K. Kim, T. Hoprasert, D. Harwood, and L. Davis. A Background Modeling and Subtraction by Codebook Construction. In IEEE International Conference on Image Processing (ICP) 2004.
• 4: Y. Ming, J. Jiang, and J. Ming. Background Modeling and Subtraction Using a Local-Linear-Dependence-Based Cauchy Statistical Model. In Proceedings of the Seventh International Conference on Digital Image Computing: Techniques and Applications, DICTA 2003: 469--478.
• 5: Y. P. Tsai, C. C. Hung, Y. P. Shih, and Zen-Chung. A Bayesian Approach to Video Object Segmentation via Merging 3-D Watershed Volumes. In IEEE Transactions on Circuits and Systems for Video Technology, Vol. 15, No. 1, January 2005.
• 6: V. Mezaris, I. Kompatsiaris, and M. G. Strintzis. Video Object Segmentation Using Bayes-Based Temporal Tracking and Trajectory Based Region Merging. In IEEE Transactions on Circuits and Systems for Video Technology, Vol. 14, No. 6, June 2004.
• 7: Z. Zivkovic. Improved Adaptive Gaussian Mixture Model for Background Subtraction. In Proceedings ICPR, 2004.
• 8: M. Karaman, L. Goldmann, D. Yu, and T. Sikora. Comparison of Static Background Segmentation Methods. In Proceedings of the SPIE, Volume 5960, pp 2140--2151, july 2005.
• 9: R Cucchiara, P. Onfiani, A. Prati, and Scarabottolo. Segmentation of Moving Objects at Frame: A Dedicated Hardware Solution. In Image Processing and its Applications, Conference Publication N. o 465, IEE, 1999.
• 10: J. Kim, T. Chen. A VLSI Architecture for Video-Object Segmentation. In IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 1, January 2003.
• 11: A. L. Printes. Circuito Integrado para Extração de Fundo não Homogêneo de Imagens Dinâmicas em Tempo Real. Master Thesis, Federal University of Campina Grande, Electrical Engineer Department, Paraíba, Brazil, December 2002.
• 12: J. P. Oliveira. Implementação em Hardware de um Sistema para Extração de Objetos de um Fundo não Homogêneo em Tempo Real. Master Thesis, Federal University of Campina Grande, Electrical Engineer Department, Paraíba, Brazil, September 2003.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Control design

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Data-path design

  I. Computing Methodologies
  I.4 IMAGE PROCESSING AND COMPUTER VISION
      I.4.6 Segmentation
          Subjects: Pixel classification

General Terms:
Algorithms, Design, Languages

Keywords:
FPGA, background subtraction, real time