REDEFIS: a system with a redefinable instruction set processor

ABSTRACT

The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight performance or power constraints, or too complex to design in short TAT/TTM. REDEFIS is a HW/SW design platform for high level, efficient implementation of ASIPs/engines for SoC systems. It is composed of a reconfigurable instruction-set processor, capable to redefine its ISA according to the user application written in high level C language, and a set of design tools (an ISA Generator and a retargetable compiler). These processors can be used as flexible engines in embedded MPSoC systems, where its ISA is fully customized and design is done at high level C (no HDL writing is necessary). In this paper we present the Redefis design platform and an implementation of our dynamically reconfigurable ISA processor (codename Vulcan). Our results demonstrate the effectiveness of the system for encryption and bitwise applications.

REFERENCES

• 1: T. Hashinaga et al. "Vulcan: the first implementation of Redefis processor and its design tool chain", Technical Report of IEICE - Subject: Reconfigurable Systems, Dec. 2004 (In Japanese).
• 2: M. Shuto et al. "Redefis: a SoC Design Platform", Technical Report of IEICE - Subject: Reconfigurable Systems, Dec. 2004 (In Japanese).
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• 13: NIST FIPS PUB 46-3, "Data Encryption Standard (DES)", http://csrc.nits.org/publications/fips/fips46/fips46-3. pdf, Oct. 1999.
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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Adaptable architectures

Additional Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

General Terms:
Design, Performance

Keywords:
ISA customization, SoC, dynamically reconfigurable processor, high performance, low power