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Robust low power computing in the nanoscale era
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Proceedings of the 19th annual symposium on Integrated circuits and systems design table of contents
Ouro Preto, MG, Brazil
TUTORIAL SESSION: Tutorials table of contents
Pages: 6 - 6  
Year of Publication: 2006
ISBN:1-59593-479-0
Author
Todd Austin  University of Michigan
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

This tutorial will present recent results in robust low power computing. The perspective will be microarchitectural: what limitations does it put on the microarchitecture and what can the microarchitect do to reduce the dependency on power and improve robustness? The tutorial will start with a technology overview that charts future trends in power and reliability. We will present a summary of prior research in dynamic power reduction in microarchitectures, and give some examples of industrial solutions. We will also review prior research in microarchitectural reduction of leakage performed by us and others. While the continued scaling that Moore's Law predicts is in many ways good for reducing power, scaling also reduces reliability by increasing uncertainty in device performance. Therefore, in order to take advantage of scaling, it will be necessary to compute in the presence of various types of silicon-related faults. Two that are particularly important are single-event upsets, and, even more serious, gates that will not meet their specifications. We will review techniques to provide robustness in light of these trends. In particular, we will revisit techniques developed by the fault-tolerant community as well as newer ideas in timing speculation, exemplified by our Razor research.The tutorial is intended for computer architects and circuit designers interested in a better understanding of current reliability challenges and emerging technologies to address them.