Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration

ABSTRACT

Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. This feature enables the substitution of the reconfigurable architecture within a configuration area on the chip. Beneficial here is that the architecture can be adapted to the actual demand of an application while run-time. High performance, flexibility and adaptivity of these devices raise the interest in academic research and also in industrial fields of application. This new method for designing systems isn't supported very well by tools until now. This tutorial should help designers as well as researchers in developing dynamic and partial reconfigurable systems and increase the number of area of applications exploiting this very promising methodology. As an example the design of an on-demand reconfigurable system for inner cabin automotive application will be presented.

REFERENCES

• 1: J. Becker, M. Hübner, M. Ullmann: "Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations", VLSI03, Darmstadt, Sep. 03
• 2: M. Ullmann, M. Huebner, B. Grimm, J. Becker: "An FPGA Run-Time System for Dynamical On-Demand Reconfiguration", RAW04, Santa Fee
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles

General Terms:
Design

Keywords:
designflow, dynamic and partial reconfiguration, reconfigurable hardware