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Fault-tolerant semifast implementations of atomic read/write registers
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Source ACM Symposium on Parallel Algorithms and Architectures archive
Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures table of contents
Cambridge, Massachusetts, USA
SESSION: Caches, registers and load balancing table of contents
Pages: 281 - 290  
Year of Publication: 2006
ISBN:1-59593-452-9
Authors
Chryssis Georgiou  University of Cyprus, Cyprus
Nicolas C. Nicolaou  University of Connecticut
Alexander A. Shvartsman  University of Connecticut and MIT
Sponsors
ACM: Association for Computing Machinery
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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ABSTRACT

This paper investigates time-efficient implementations of atomic read-write registers in message-passing systems where the number of readers can be unbounded. In particular we study the case of a single writer, multiple readers, and S servers, such that the writer, any subset of the readers, and up to t servers may crash. A recent result of Dutta et al. [3] shows how to obtain fast implementations in which both reads and writes complete in one communication round-trip, under the constraint that the number of readers is less than S<over>t - 2, where t < S<over>2 . In that same paper the authors pose a question of whether it is possible to relax the bound on readers, and at what cost, if semifast implementations are considered, i.e., implementations that have fast reads or fast writes.This paper provides an answer to this question. It is shown that one can obtain implementations where all writes are fast, i.e., involving a single round-trip communication, and where reads complete in one to two communication rounds under the assumption that no more than t < S<over>2 servers crash. Simulated scenarios included in this paper indicate that only a small fraction of reads require a second communication round. Interestingly the correctness of the implementation does not depend on the number of concurrent readers in the system. The solution is obtained with the help of non-unique virtual ids assigned to each reader, where the readers sharing a virtual id form a virtual node. For the proposed definition of semifast implementations it is shown that implementations satisfying certain assumptions are semifast if and only if the number of virtual ids in the system is less than S<over>t - 2. This result is proved to be tight in terms of the required communication. It is shown that only a single complete two-round read operation may be necessary for each write operation. It is furthermore shown that no semifast implementation exists for the multi-reader, multi-writer model.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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S. Dolev, S. Gilbert, N. Lynch, A. Shvartsman, and J. Welch. Geoquorums: Implementing atomic memory in mobile ad hoc networks, 2003.
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C. Georgiou, N. Nicolaou, and A. Shvartsman. Fault-tolerant semifast implementations for atomic read/write registers, 2005. http://www.cse.uconn.edu/ ncn03001/pubs/TRs/GNS06.pdf.
 
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P. Vitanyi and B. Awerbuch. Atomic shared register access by asynchronous hardware. In 27th Annual IEEE Symposium on Foundations of Computer Science, pages 233--243, 1986.


Collaborative Colleagues:
Chryssis Georgiou: colleagues
Nicolas C. Nicolaou: colleagues
Alexander A. Shvartsman: colleagues