Visibility enhancement for silicon debug

ABSTRACT

Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require the instrumentation of on-chip logic for extracting the internal register data from in situ silicon. Unfortunately, lack of visibility of the combinational network values impedes the ability to functionally debug the silicon part. Visibility enhancement techniques enable the virtual observation of combinational nodes with minimal computational overhead. These techniques also cover the register selection analysis for DFD and multi-level design abstraction correlation for viewing values at the register transfer level (RTL). Experimental results show that visibility enhancement techniques can leverage a small amount of extracted data to provide a high amount of computed combinational signal data. Visibility enhancement provides the needed connection between data obtained from the DFD logic and HDL simulation-related debug systems.

REFERENCES

• 1: Smith, Gary. "ASIC Design Times Spiral Out of Control: User Wants and Needs", Gartner, Inc., January 29, 2002. p.4--12
• 2: Smith, Gary; Tan, Sharon. "Conservative Times, Conservative Designs in EDA: User Wants and Needs", Gartner, Inc., February 10, 2004. p.6--17
• 3: Hong Hao , Rick Avra, Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation, Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test, p.175-183, October 21-25, 1995
• 4: Bart Vermeulen , Steven Oostdijk , Frank Bouwman, Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip, Proceedings of the IEEE International Test Conference 2001, p.121-130, October 30-November 01, 2001
• 5: Goering, Richard. "Scan design called portal for hackers". EE Times. October 25, 2004
• 6: E. J. McCluskey , Ahmad Al-Yamani , James C. -M Li , Chao-Wen Tseng , Erik Volkerink , Francois-Fabien Ferhani , Edward Li , Subhasish Mitra, ELF-Murphy Data on Defects and Test Sets, Proceedings of the 22nd IEEE VLSI Test Symposium, p.16, April 25-29, 2004
• 7: "International Technology Roadmap for Semiconductors" 2003, p. 15.
• 8: Wilson, Ron. "Silicon Debug Tools Lengthen Their Reach". EE Times. July 17, 2003.
• 9: Valeria Bertacco , Maurizio Damiani , Stefano Quer, Cycle-based symbolic simulation of gate-level synchronous circuits, Proceedings of the 36th ACM/IEEE conference on Design automation, p.391-396, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309966]
• 10: Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
• 11: Malay K. Ganai , Adnan Aziz , Andreas Kuehlmann, Enhancing simulation with BDDs and ATPG, Proceedings of the 36th ACM/IEEE conference on Design automation, p.385-390, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309965]
• 12: Yu-Chin Hsu , Bassam Tabbara , Yirng-An Chen , Furshing Tsai, Advanced techniques for RTL debugging, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775927]
• 13: Jerry R. Burch , Vigyan Singhal, Robust latch mapping for combinational equivalence checking, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.563-569, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289087]
• 14: Demos Anastasakis , Robert Damiano , Hi-Keung Tony Ma , Ted Stanion, A practical and efficient method for compare-point matching, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.513997]
• 15: Jason T. L. Wang , Kaizhong Zhang , Gung-Wei Chirn, Algorithms for approximate graph matching, Information Sciences—Informatics and Computer Science: An International Journal, v.82 n.1-2, p.45-74, Jan. 1995 [doi>10.1016/0020-0255(94)00057-I]
• 16: Bart Vermeulen , Mohammad Z. Urfianto , Sandeep K. Goel, Automatic generation of breakpoint hardware for silicon debug, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996708]
• 17: Miron Abramovici , Paul Bradley , Kumar Dwarakanath , Peter Levin , Gerard Memmi , Dave Miller, A reconfigurable design-for-debug infrastructure for SoCs, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1146916]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING

General Terms:
Design, Verification

Keywords:
functional verification, silicon debug, silicon validation