| Crosstalk-aware domino logic synthesis |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Munich, Germany
SESSION: Progress in logic and arithmetic circuit optimisation
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Pages: 1312 - 1317
Year of Publication: 2006
ISBN:3-9810801-0-6
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European Design and Automation Association
3001 Leuven, Belgium, Belgium
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Downloads (6 Weeks): 2, Downloads (12 Months): 7, Citation Count: 0
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ABSTRACT
We propose a logic synthesis flow which utilizes the functionality of circuit to synthesize a domino-cell network which will have more wires crosstalk-immune to each other. For that purpose, techniques of output phase flipping and crosstalk-aware technology mapping are used. Meanwhile, metric to measure the crosstalk sensitivity of domino cells in synthesis level is proposed. Experimental results demonstrate that the crosstalk sensitivity of the synthesized domino-cell network is greatly reduced by 51% using our synthesis flow as compared with conventional methodology. Furthermore, after placement and routing are performed, the ratio of the number of crosstalk-immune wire pairs to the number of total wire pairs is about 25% using our methodology as compared to 9% using conventional techniques.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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A. Vittal, M. Marek-Sadowska, "Crosstalk reduction for VLSI", IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp.290--298, vol.16, i.3, March 1997.
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2
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D. Harris, T. Grutkowski, "Advanced Domino Circuit Design", Tutorial Note, DATE, 2004.
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3
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Y. Im, K. Roy, "A Logic-aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits", ISCAS, pp.637--640, 2003.
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4
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5
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6
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J. Lou, W. Chen, "Crosstalk-aware Placement", IEEE Trans. Design and Test of Computers, pp.24--32, vol.21, i.1, Jan.-Feb. 2004.
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7
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8
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Ruchir Puri , Andrew Bjorksten , Thomas E. Rosser, Logic optimization by output phase assignment in dynamic logic synthesis, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.2-7, November 10-14, 1996, San Jose, California, United States
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9
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M. Zhao, S. S. Sapatnekar, "Dual-monotonic Domino Gate Mapping and Optimal Output Phase Assignment of Domino Logic", ISCAS, pp.309--312, May. 2000.
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10
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F. F. Sellers, M. Y. Hsiao, L. W. Bearnson, "Analyzing Errors with the Boolean Difference", IEEE Trans. Computers, pp.676--683, vol. C-17, no.7, July 1968.
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11
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E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, A. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis", Electronics Research Laboratory, Memorandum No. UCB/ERL M92/41, 4 May 1992.
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12
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13
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14
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15
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16
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M. R. Prasad, D. Kirkpatrick, R. K. Brayton, "Domino Logic Synthesis and Technology Mapping", Intl. Workshop on Logic Synthesis(IWLS), 1997.
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18
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K. W. Kim, S. M. Kang, "Crosstalk Noise Minimization in Domino Logic Design", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.20, no.9, pp.1091--1100, Sep. 2001.
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