| Efficient unknown blocking using LFSR reseeding |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Munich, Germany
SESSION: Interactive presentations
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Pages: 1051 - 1052
Year of Publication: 2006
ISBN:3-9810801-0-6
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European Design and Automation Association
3001 Leuven, Belgium, Belgium
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Downloads (6 Weeks): 1, Downloads (12 Months): 11, Citation Count: 2
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ABSTRACT
This paper presents an efficient method to block unknown values from entering temporal compactors. The control signals for the blocking logic are generated by an LFSR. The proposed technique minimizes the size of the LFSR by propagating only one fault effect for each fault and balancing the number of specified bits in each control pattern. The linear solver to find seeds of the LFSR intelligently chooses a solution such that the impact on test quality is minimal. Experimental results show that sizes of control data for the proposed method are smaller than prior work and run time of the proposed method is several orders of magnitude smaller than that of prior work. Hardware overhead is very low.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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M. Naruse, I. Pomeranz, S. M. Reddy, and S. Kundu. On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. In Proceedings of IEEE International Test Conference, pages 1060--1068, 2003.
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Januz Rajki , Jerzy Tyzer , Mark Kassab , Nilanjan Mukherjee , Rob Thompson , Kun-Han Tsai , Andre Hertwig , Nagesh Tamarapalli , Grzegorz Mrugalski , Geir Eide , Jun Qian, Embedded Deterministic Test for Low-Cost Manufacturing Test, Proceedings of the 2002 IEEE International Test Conference, p.301, October 07-10, 2002
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Huaxing Tang , Chen Wang , Janusz Rajski , Sudhakar M. Reddy , Jerzy Tyszer , Irith Pomeranz, On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios, Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), p.59-64, January 03-07, 2005
[doi> 10.1109/ICVD.2005.127]
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Yuyi Tang , Hans-Joachim Wunderlich , Harald Vranken , Friedrich Hapke , Michael Wittke , Piet Engelke , Ilia Polian , Bernd Becker, X-Masking During Logic BIST and Its Impact on Defect Coverage, Proceedings of the International Test Conference on International Test Conference, p.442-451, October 26-28, 2004
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CITED BY 2
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Mango C.-T. Chao , Kwang-Ting Cheng , Seongmoon Wang , Srimat T. Chakradhar , Wen-Long Wei, A hybrid scheme for compacting test responses with unknown values, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
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