Classification trees for random tests and functional coverage

ABSTRACT

This article presents the classification tree method for functional verification to close the gap from the specification of a test plan to SystemVerilog [2] testbench generation. Our method supports the systematic development of test configurations and is based on the classification tree method for embedded systems (CTM/ES) [1] extending CTM/ES for random test generation as well as for functional coverage and property specification. We support the structured coding of assertions and constraints by a two-step method: (i) creation of the classification tree (ii) creation of (sample) abstract test sequences. For SystemVerilog testbench generation, we introduce a mapping to SystemVerilog random tests, assertions, and functional coverage specifications. As our method is derived from the CTM/ES, it is also compliant to the V-method and thus applies to IEC61508-conformant development of electronic safety related systems. The remainder of this paper gives an overview of the classification tree method (CTM) before presenting our extension for functional verification.

REFERENCES

• 1: Mirko Conrad. Modell-basierter Test eingebetteter Software im Automobil. Deutscher Universitäts-Verlag, Wiesbaden, 2004.
• 2: IEEE. IEEE Std.1800-2005 - Standard for SystemVerilog Unified Hardware Design, Specification and Verification Language, November 2005.
• 3: Klaus Lamberg and Michael Beine. Test methods and tools in model-based function development. In ASIM, Fachtagung Simulations- und Testmethoden für Software in Fahrzeugsystemen, March 2005.