| Arbitrary design of high order noise transfer function for a novel class of reduced-sample-rate sigma-delta-pipeline ADCs |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Munich, Germany
SESSION: Methods and tools for systematic analogue design
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Pages: 138 - 143
Year of Publication: 2006
ISBN:3-9810801-0-6
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European Design and Automation Association
3001 Leuven, Belgium, Belgium
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Downloads (6 Weeks): 2, Downloads (12 Months): 14, Citation Count: 0
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ABSTRACT
A novel noise transfer function (NTF) for high order reduced-sample-rate sigma-delta-pipeline (SDP) ADCs is presented. The proposed NTF determines the location of the non-zero poles improving the stabilization of the loop and implementing the reduced-sample-rate structure, concurrently. A design methodology based on simulated-annealing-algorithm is developed to design the optimum NTF. To verify the usefulness of the proposed NTF and design procedure, two different modulators are presented. Simulation results show that with a 4th order modulator, designed making use of the proposed approach, the maximum SNDR of 115dB and 124.1dB can be achieved with only OSR of 8, and 16 respectively.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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A. Bosi, A. Panigada, G. Cesura, and R. Castello, "An 80MHz 4 X Oversampled Cascaded ΔΣ -pipelined ADC with 75dB DR and 87dB SFDR," ISSCC 2005, Session 9, Switched-Capacitor ΔΣ Modulators, 9.5.
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2
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W. Qin, B. Hu and X. Ling, "Sigma-delta ADC with reduced sample rate multibit quantizer," IEEE Trans. Circuits Syst. II, vol. 40, pp. 824--828, June 1999.
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3
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L. Lo Presti, "Efficient modified-sinc filters for sigma-delta A/D converters," IEEE Trans. Circuits Syst. II, vol. 47, pp. 1024--1213, Nov 2000.
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4
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J. Marrkus and G. Temes, "An Efficient Architecture for Low Oversampling Ratios," IEEE Trans. Circuits Syst. I, vol. 51, no. 1, January 2004.
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5
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R. Schreier, "Delta-Sigma Toolbox, available: http://www.mathworks/matlabcentral/fileexchange
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6
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J. G. Kenny, and L. R. carely, "CLANS: a high-level synthesis tool for high resolution data converters," Int. Conf. on Computer Aided-Design, vol. 1, Nov. 1988.
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M. Yavari, O. Shoaei, "Low-Voltage Sigma-Delta Modulator Topologies for Broadband Communications Applications" IEICE Transactions on Electronics, vol. E87-C, no. 6, Jun 2004.
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P. Kiss et al., "Adaptive Digital Correction of Analog Errors in MASH ADC's-Part II: Correction Using Test-Signal Injection," IEEE Trans. Circuits Syst. II, vol. 47, no. 7, pp. 629--638, July, 2000.
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10
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J. Koh, Y. Choi, and G. Gomez, "A 66dB DR 1.2V 1.2 mW Single-Amplifier Double-Sampling 2nd-order ΔΣ ADC for WCDMA in 90nm CMOS," ISSCC2005, Session 9, Switched-Capacitor ΔΣ Modulators, 9.3.
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