Functionality directed clustering for low power MTCMOS design

ABSTRACT

Multi-Threshold CMOS (MTCMOS) is a circuit style that can effectively reduce leakage power consumption. Sleep transistor sizing is the key issue when MTCMOS circuit is designed. If the sleep transistor size is too large, the circuit performance can be maintained but the dynamic power consumption of the sleep transistor will increase. On the other hand, if the sleep transistor size is too small, there will be significant performance degradation because of the increased resistance to ground. Previous approach [1, 2] designed the sleep transistor size based on mutual exclusive discharge patterns. However, these approaches considered only topology of a circuit. We observed that two possible simultaneous switching gates may not discharge at the same time in terms of functionality. Thus, we propose an algorithm to determine how to cluster cells to share sleep transistors taking both topology and functionality into consideration. The results show that the proposed method can achieve on the average 18% reduction ratio in terms of the number of sleep transistors as compared to the method without considering functionality.

REFERENCES

• 1: James Kao , Siva Narendra , Anantha Chandrakasan, MTCMOS hierarchical sizing based on mutual exclusive discharge patterns, Proceedings of the 35th annual conference on Design automation, p.495-500, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277180]
• 2: Mohab Anis , Mohamed Mahmoud , Mohamed Elmasry , Shawki Areibi, Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514041]
• 3: Shekhar Borkar, Low power design challenges for the decade (invited talk), Proceedings of the 2001 conference on Asia South Pacific design automation, p.293-296, January 2001, Yokohama, Japan [doi>10.1145/370155.370356]
• 4: Yen-Te Ho , Ting-Ting Hwang, Low power design using dual threshold voltage, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.205-208, January 27-30, 2004, Yokohama, Japan
• 5: S. Muth, T. Douseki, T. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS," IEEE Journal of Solid-State Circuits, vol. 30, no. 8, pp. 847--853, Feb. 1995.
• 6: James Kao , Anantha Chandrakasan , Dimitri Antoniadis, Transistor sizing issues and tool for multi-threshold CMOS technology, Proceedings of the 34th annual conference on Design automation, p.409-414, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266182]
• 7: Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj, "Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 998--1012, 1995.