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Simultaneous floorplanning and resource binding: a probabilistic approach
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: High-level synthesis table of contents
Pages: 517 - 522  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Azadeh Davoodi  University of Maryland, College Park, MD
Ankur Srivastava  University of Maryland, College Park, MD
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this work we present a probabilistic approach to simultaneous floorplanning and resource binding for low power. Traditional approaches iteratively perform floorplanning and resource binding while using crude deterministic wire-length estimates like bounding box (since we do not have routing information for inter module inter-connect). Non-availability of accurate wire-length results in suboptimal design and failure of timing closure. In this work we model the wire-lengths as probability distributions and propose a novel probabilistic optimization methodology. Experimental results using state of the art commercial and academic tools were conducted. The novelty in this work is in the higher chance of ending with a feasible design that is synthesizable without losing in overall power (interconnect + module + register). Experimental results show that on-average the number of unsynthesized modules after routing for Mediabench benchmarks were 2 in the conventional case, while on average our probabilistic approach had all modules synthesized after routing.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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A. Srivastava E. Kursun and M. Sarrafzadeh. "Predictability Driven Binding: Methodologies and Tradeoffs". In Journal of Circuits, Systems and Computers, Special Issue on Low Power IC Designs, 2002.
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S. Adya, I. Markov. "Fixed-outline Floorplanning Through Better Local Search". In Proc. of ACM/IEEE International Conference Computer Design, pages 321--334, 2001.
Collaborative Colleagues:
Azadeh Davoodi: colleagues
Ankur Srivastava: colleagues