| TAPHS: thermal-aware unified physical-level and high-level synthesis |
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Asia and South Pacific Design Automation Conference
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Proceedings of the 2006 Asia and South Pacific Design Automation Conference
table of contents
Yokohama, Japan
SESSION: High-level synthesis
table of contents
Pages: 879 - 885
Year of Publication: 2006
ISBN:0-7803-9451-8
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Authors
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Zhenyu (Peter) Gu
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Northwestern University, Evanston, IL
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Yonghong Yang
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Queen's University, Kingston, ON, Canada
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Jia Wang
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Northwestern University, Evanston, IL
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Robert P. Dick
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Northwestern University, Evanston, IL
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Li Shang
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Queen's University, Kingston, ON, Canada
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IEEE Press
Piscataway, NJ, USA
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| Bibliometrics |
Downloads (6 Weeks): 5, Downloads (12 Months): 42, Citation Count: 7
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ABSTRACT
Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performance. It is necessary to consider thermal effects during all levels of the design process, from the architectural level to the physical level. However, design-time temperature prediction requires access to block placement, wire models, power profile, and a chip-package thermal model. Thermal-aware design and synthesis necessarily couple architectural-level design decisions (e.g., scheduling) with physical design (e.g., floorplanning) and modeling (e.g., wire and thermal modeling).This article proposes an efficient and accurate thermal-aware floorplanning high-level synthesis system that makes use of integrated high-level and physical-level thermal optimization techniques. Voltage islands are automatically generated via novel slack distribution and voltage partitioning algorithms in order to reduce the design's power consumption and peak temperature. A new thermal-aware floorplanning technique is proposed to balance chip thermal profile, thereby further reducing peak temperature. The proposed system was used to synthesize a number of benchmarks, yielding numerous designs that trade off peak temperature, integrated circuit area, and power consumption. The proposed techniques reduces peak temperature by 12.5°C on average. When used to minimize peak temperature with a fixed area, peak temperature reductions are common. Under a constraint on peak temperature, integrated circuit area is reduced by 9.9% on average.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 7
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Yonghong Yang , Zhenyu (Peter) Gu , Changyun Zhu , Li Shang , Robert P. Dick, Adaptive chip-package thermal analysis for synthesis and design, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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