Monotonic parallel and orthogonal routing for single-layer ball grid array packages

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Monotonic parallel and orthogonal routing for single-layer ball grid array packages

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2006 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

SESSION: New routing techniques table of contents

Pages: 642 - 647

Year of Publication: 2006

ISBN:0-7803-9451-8

Authors

Yoichi Tomioka	Tokyo Institute of Technology, Meguro-ku, Tokyo, Japan
Atsushi Takahashi	Tokyo Institute of Technology, Meguro-ku, Tokyo, Japan

Sponsors

: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IPSJ SIG-SLDM : Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 22, Citation Count: 4

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ABSTRACT

In this paper, we give the necessary and sufficient condition that all nets can be connected by monotonic routes when a net consists of a finger and a ball and fingers are on the two parallel boundaries of the Ball Grid Array package, and propose a monotonic routing method based on this condition. Moreover, we give a necessary condition and a sufficient condition when fingers are on the two orthogonal boundaries, and propose a monotonic routing method based on the necessary condition.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	4	S. Shibata, K. Ukai, N. Togawa, M. Sato, and T. Ohtsuki, "A BGA Package Routing Algorithm on Sketch Layout System," The journal of Japan Institute for Interconnecting and Packaging Electronic Circuits, vol. 12, no. 4, pp. 241--246, 1997. (In Japanese).
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	6	C.-C. Tsai, C.-M. Wang, and S.-J. Chen, "NEWS: A Net-Even-Wiring System for the Routing on a Multilayer PGA Package," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 2, pp. 182--189, 1998.
	7	An Even Wiring Approach to the Ball Grid Array Package Routing, Proceedings of the 1999 IEEE International Conference on Computer Design, p.303, October 10-13, 1999

CITED BY 5

	Lijuan Luo , Martin D. F. Wong, Ordered escape routing based on Boolean satisfiability, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Jin-Tai Yan , Zhi-Wei Chen, RDL pre-assignment routing for flip-chip designs, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA
	Jia-Wei Fang , Chin-Hsiung Hsu , Yao-Wen Chang, An integer linear programming based routing algorithm for flip-chip design, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Lijuan Luo , Martin D. F. Wong, On using SAT to ordered escape problems, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Jin-Tai Yan , Zhi-Wei Chen, IO connection assignment and RDL routing for flip-chip designs, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan