Test and recovery for fine-grained nanoscale architectures

ABSTRACT

The nanoscale devices are assumed to include up to 10¹² devices/cm² and they also include high defect densities of up to 10%, hence new test strategies are required to efficiently test and diagnose these devices in parallel with low number of test configurations and test architectures. This paper presents built-in self-test (BIST) and recovery increase procedures for molecular electronic devices. The proposed BIST procedure is a fine-grained technique that tests the nanoBlocks and switchBlocks in a nanoscale device. The nano device under test is divided into test groups each containing two nanoBlocks, i.e. test pattern generator (PG) and response generator (RG), and a switchBlock between these two nanoBlocks. Due to high defect density of nano devices, an efficient diagnostic procedure is required to be done after BIST procedure to achieve high recovery. The recovery is defined as the total number of obtained fault-free blocks using a test procedure to the total number of available fault-free blocks on a chip. The proposed recovery increase procedure increases the number of fault-free components by finding the location of faulty/fault-free blocks in a faulty test group in a tested device. Finally a defect map is created to be used by programming devices during configuration of the nanoFabric to avoid defective components. This results in a reliable system constructed using unreliable components. The proposed BIST procedure provides a complete coverage of the modeled faults (e.g. stuck-at, stuck-open, bridging, forward and reverse-biased diodes) and our simulation results show high recovery achieved using recovery increase procedure.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.3 Reliability and Testing**