ACM Home Page
Please provide us with feedback. Feedback
A provably good algorithm for high performance bus routing
Full text PdfPdf (928 KB)
Source International Conference on Computer Aided Design archive
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design table of contents
Pages: 830 - 837  
Year of Publication: 2004
ISBN:0-7803-8702-3
Authors
M. M. Ozdal  Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
M. D. F. Wong  Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
Publisher
IEEE Computer Society  Washington, DC, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 11,   Citation Count: 2
Additional Information:

abstract   references   cited by   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: 10.1109/ICCAD.2004.1382690

ABSTRACT

As the clock frequencies used in industrial applications increase, the timing requirements on routing problems become tighter, and current routing tools can not successfully handle these constraints any more. We focus on the high-performance single-layer bus routing problem, where the objective is to match the lengths of all nets belonging to each bus. An effective approach to solve this problem is to allocate extra routing resources around short nets during routing; and use those resources for length extension afterwards. We first propose a provably optimal algorithm for routing nets with min-area max-length constraints. Then, we extend this algorithm to the case where minimum constraints are given as exact length bounds. We also prove that this algorithm is optimal within a constant factor. Both algorithms proposed are also shown to be scalable for large circuits, since the respective time complexities are O(A) and O(A log A), where A is the area of the intermediate region between chips.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
[2] K. D. Boese, J. Cong, A. B. Kahng, K. S. Leung, and D. Zhou. On highspeed VLSI interconnects: Analysis and design. In Proc. Asia-Pacific Conf. Circuits Syst., 1992.
 
3
[3] J. Cong, A. B. Kahng, G. Robins, M, Sarrafzadeh, and C. K. Wong. Provably good performance-driven global routing. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 11(6): 739-752, 1992.
 
4
 
5
 
6
 
7
[7] E. Kuh, M. A. B. Jackson, and M. Marek-Sadowska. Timing-driven routing for building block layout. In Proc. IEEE Intl. Symposium on Circuits and Systems, pages 518-519, 1987.
 
8
[8] S. Lee and M. D. F. Wong. Timing-driven routing for fpgas based on lagrangian relaxation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 506-510, 2003.
 
9
[9] C. E. Leiserson and R. Y. Pinter. Optimal placement for river routing. In Proc. of the CMU Conf. on VLSI Systems and Computations, 1981.
 
10
 
11
[11] J. Ludwig. IBM Systems Group. Private communication, 2004.
 
12
[12] M. M. Ozdal and M. D. F. Wong. An algorithmic study of single-layer bus routing for high-speed boards. Manuscript.
 
13
 
14
 
15
[15] R. Y. Pinter. River routing: Methodology and analysis. In Proc. of the 3rd Caltech Conf. on VLSI, 1983.
 
16
[16] S. Prastjutrakul and W. J. Kubitz. A timing-driven global router for custom chip design. In Proc. of IEEE Intl. Conf. on Computer-Aided Design, pages 48-51, 1990.
 
17
[17] L. W. Ritchey. Busses: What are they and how do they work? Printed Circuit Design Magazine, 2000.
18

Collaborative Colleagues:
M. M. Ozdal: colleagues
M. D. F. Wong: colleagues