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An analytic placer for mixed-size placement and timing-driven placement
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Source International Conference on Computer Aided Design archive
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design table of contents
Pages: 565 - 572  
Year of Publication: 2004
ISBN:0-7803-8702-3
Authors
A. B. Kahng  Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
Q. Wang  Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
Publisher
IEEE Computer Society  Washington, DC, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 52,   Citation Count: 14
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abstract   references   cited by   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: 10.1109/ICCAD.2004.1382641

ABSTRACT

We extend the APlace wirelength-driven standard-cell analytic placement framework of A.A. Kennings and I.L. Markov (2002) to address timing-driven and mixed-size ("boulders and dust") placement. Compared with timing-driven industry tools, evaluated by commercial detailed routing and STA, we achieve an average of 8.4% reduction in cycle time and 7.5% reduction in wirelength for a set of six industry testcases. For mixed-size placement, we achieve an average of 4% wirelength reduction on ISPD02 mixed-size placement benchmarks compared to results of the leading-edge solver, Feng Shui (v2.4) (Khatkhate et al., 2004). We are currently evaluating our placer on industry testcases that combine the challenges of timing constraints, large instance sizes, and embedded blocks (both fixed and unfixed).


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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[3] C. J. Alpert, T. Chan, A. B. Kahng, I. Markov and P. Mulet, "Faster Minimization of Linear Wirelength for Global Placement", IEEE Trans. Computer Aided Design 17(1) (1998), pp. 3-13.
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[5] R. Baldick, A. B. Kahng, A. Kennings and I. L. Markov, "Function Smoothing with Applications to VLSI Layout", Proc. Asia and South Pacific Design Automation Conf., Jan. 1999, pp. 225-228.
 
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[6] Web site of VLSI CAD Bookshelf. http://www.gigascale.org/bookshelf/.
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[17] D. Hill, "Method and System for High Speed Detailed Placement of Cells within an Integrated Circuit Design", US Patent 6370673, April 2002.
 
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[18] Web site of ISPD02 Mixed-Size Placement Benchmarks. http://vlsicad.eecs.umich.edu/BK/ ISPD02bench/.
 
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[19] Web site of ISPD 2001 Circuit Benchmarks. http://nthucad.cs.nthu.edu.tw/~ycchou/ benchmark/placement.htm.
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[23] A. A. Kennings and I. L. Markov, "Smoothening Max-terms and Analytical Minimization of Half-Perimeter Wirelength", VLSI Design 14(3) (2002), pp. 229-237.
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[27] C. Li and C.-K. Koh, "On Improving Recursive Bipartitioning-Based Placement", Technical Report TRECE-03-14, Purdue Univ., 2003.
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[31] W. Naylor et al., "Non-Linear Optimization System and Method for Wire Length and Delay Optimization for an Automatic Electric Circuit Placer", US Patent 6301693, Oct. 2001.
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