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Variability inspired implementation selection problem
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Source International Conference on Computer Aided Design archive
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design table of contents
Pages: 423 - 427  
Year of Publication: 2004
ISBN:0-7803-8702-3
Authors
A. Davoodi  Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
V. Khandelwal  Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
A. Srivastava  Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
Publisher
IEEE Computer Society  Washington, DC, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 5,   Citation Count: 7
Additional Information:

abstract   references   cited by   collaborative colleagues  

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DOI Bookmark: 10.1109/ICCAD.2004.1382612

ABSTRACT

Given a directed acyclic graph and different possible implementations for each node, the implementation selection problem (ISP) selects the appropriate implementation for each node such that a given global design objective is optimized, ISP is a generic formulation that is explicitly or implicitly solved in several design automation problems like leakage optimization using dual V/sub th/, gate sizing, etc. An implementation of a node results in an associated delay and perhaps cost for the node. In the presence of different sources of uncertainty and fabrication variability, fixed estimates of delays and costs of a node are extremely erroneous. We investigate a probabilistic approach to solve ISP by considering probability density functions for delays and costs of a node. We propose a dynamic-programming based approach in a probabilistic sense and introduce effective pruning criteria when dealing with probability distributions for identifying co-optimal solution at each stage. A case study of leakage optimization using dual V/sub th/ is presented where we show the effectiveness of a probabilistic approach considering V/sub th/ variability over a traditional deterministic one.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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[5] A. Srivastava E. Kursun and M. Sarrafzadeh. "Predictability Driven Binding: Methodologies and Tradeoffs". In Journal of Circuits, Systems and Computers, Special Issue on Low Power IC Designs, 2002.
 
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[8] S. Mutah, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada. "I-V Power Supply High-speed Digital Circuit Technology with Multi Threshold Voltage CMOS". In Processings of IEEE Journal of Solid-State Circuits, pages 847-853, August 1995.
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[10] T. Kuroda. "A 0.9 v 150 MHz 10MW 4mm2 2-d discrete cosine transform core processor with variable threshold voltage scheme". In Proc. of IEEE Journal of Solid-State Circuits, pages 1770-1779, Novemebr 1996.

CITED BY  7
 
 
 
 
 
Collaborative Colleagues:
A. Davoodi: colleagues
V. Khandelwal: colleagues
A. Srivastava: colleagues