Going beyond TMR for protection against multiple faults

ABSTRACT

Future technologies will present devices so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. Since many soft errors might appear at the same time, classical fault tolerance techniques, such as TMR, will no longer provide reliable protection and will make new design approaches necessary. This study shows that the TMR approach has intrinsic weaknesses that impair its effectiveness in the presence of multiple faults, and proposes a new technique that provides better protection than TMR for single as well as multiple faults. The proposed technique is based on the use of some analog components among the digital circuits. We present results based on a multiplier, and show that the technique is scalable to withstand higher quantities of simultaneous faults.

REFERENCES

• 1: L. Anghel , D. Alexandrescu , M. Nicolaidis, Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy, Proceedings of the 13th symposium on Integrated circuits and systems design, p.237, September 18-24, 2000
• 2: Lorena Anghel , Michael Nicolaidis, Cost reduction and evaluation of temporary faults detecting technique, Proceedings of the conference on Design, automation and test in Europe, p.591-598, March 27-30, 2000, Paris, France [doi>10.1145/343647.343863]
• 3: Antonio C. S. Beck Filho , Julio C. B. Mattos , Flávio R. Wagner , Luigi Carro, CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator, Proceedings of the 16th symposium on Integrated circuits and systems design, p.349, September 08-11, 2003
• 4: Cristian Constantinescu, Trends and Challenges in VLSI Circuit Reliability, IEEE Micro, v.23 n.4, p.14-19, July 2003 [doi>10.1109/MM.2003.1225959]
• 5: Don Edenfeld , Andrew B. Kahng , Mike Rodgers , Yervant Zorian, 2003 Technology Roadmap for Semiconductors, Computer, v.37 n.1, p.47-56, January 2004 [doi>10.1109/MC.2004.1260725]
• 6: Defect and Error Tolerance in the Presence of Massive Numbers of Defects, IEEE Design & Test, v.21 n.3, p.216-227, May 2004 [doi>10.1109/MDT.2004.8]
• 7: Barry W. Johnson, Design & analysis of fault tolerant digital systems, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1988
• 8: Fernanda Lima , Luigi Carro , Ricardo Reis, Designing fault tolerant systems into SRAM-based FPGAs, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775997]
• 9: C. A. L. Lisboa , L. Carro, An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets, Proceedings of the International On-Line Testing Symposium, 10th IEEE (IOLTS'04), p.180, July 12-14, 2004 [doi>10.1109/IOLTS.2004.13]
• 10: C. A. L. Lisboa , L. Carro, Arithmetic Operators Robust to Multiple Simultaneous Upsets, Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium on (DFT'04), p.289-297, October 10-13, 2004
• 11: Lisbôa, C. and Carro, L., "Highly Reliable Arithmetic Multipliers for Future Technologies", in Proceedings of the International Workshop on Dependable Embedded Systems - WDES 2004 - in conjunction with the 23rd International Symposium on Reliable Distributed Systems - SRDS 2004, pp. 13--18. Edited by Becker, L. B. and Kaiser, J., Florianópolis, October 17, 2004.
• 12: Messenger, G. C., "A Summary Review of Displacement Damage from High Energy Radiation in Silicon Semiconductors and Semiconductor Devices", IEEE Transactions on Nuclear Science, vol. 39, no. 3, pp. 468--473, IEEE Computer Society, New York-London, June 1992.
• 13: Matthias Pflanz , Heinrich Theodor Vierhaus, Online Check and Recovery Techniques for Dependable Embedded Processors, IEEE Micro, v.21 n.5, p.24-40, September 2001 [doi>10.1109/40.958697]
• 14: Alexandre Schmid , Yusuf Leblebici, A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies, Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium on (DFT'04), p.39-47, October 10-13, 2004
• 15: Semiconductor Industry Association. International Technology Roadmap for Semiconductors - ITRS 2003, last access November 12, 2004. http://public.itrs.net/Files/2003ITRS/Home2003.htm.
• 16: M. Rebaudengo, M. Sonza Reorda, M. Violante, B. Nicolescu, R. Velazco, "Coping With SEUs/SETs in Microprocessors by means of Low-Cost Solutions: A Comparative Study", IEEE Transactions on Nuclear Science, vol. 49, no. 3, pp. 1491--1495, IEEE Computer Society, New York-London, June 2002.
• 17: Townsend, W. J., Abraham, J. A. and Lala, P. K., "Online Error Detecting Constant Delay Adder", in Proceedings of the 9th IEEE International Online Testing Symposium, pp. 17--22, Kos Island, Greece, July 7-9, 2003.
• 18: Wirth, G., Vieira, M. and Kastensmidt, F. L., "Computer Efficient Modeling of SRAM Cells Sensitivity to SEU", in Proceedings of the 6th IEEE Latin America Test Workshop, pp. 51--56, Salvador, Bahia, Brazil, March 30-April 2nd, 2005.
• 19: Yang, F. L. and Saleh, R. A., "Simulation and Analysis of Transient Faults in Digital Circuits", IEEE Journal of Solid-State Circuits, vol. 27, no. 3, pp. 258--264, IEEE Computer Society, New York-London, March 1992.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Design, Experimentation, Reliability

Keywords:
design techniques, fault tolerance, future technologies, simultaneous transient faults