| Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic |
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Proceedings of the 18th annual symposium on Integrated circuits and system design
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Florianolpolis, Brazil
Pages: 62 - 67
Year of Publication: 2005
ISBN:1-59593-174-0
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Downloads (6 Weeks): 1, Downloads (12 Months): 11, Citation Count: 2
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ABSTRACT
In this paper, we propose a new approach for using Built-in Current Sensor (BICS) to detect not only transient upsets in sequential logic but also in combinational circuits. In this approach, the BICS is connected in the design bulk to increase its sensitivity to detect any current discrepancy that may occur during a charged particle strike. In addition, the proposed BICS can inform if the upset has occurred in the PMOS or NMOS transistors, which can generate a more precise evaluation of the corrupted region. The proposed approach was validated by Spice simulation. The BICS and the case-studied circuits were designed in the 100nm CMOS technology. The bulk BIC sensor detects various shapes of current pulses generated due to charged particle strike. Results show that the proposed bulk BICS presents minor penalties for the design in terms of area, performance and power consumption and it has high detection sensitivity.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Balkaran Gill , Michael Nicolaidis , Francis Wolff , Chris Papachristou , Steven Garverick, An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories, Proceedings of the conference on Design, Automation and Test in Europe, p.592-597, March 07-11, 2005
[doi> 10.1109/DATE.2005.54]
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Wirth, G., Vieira, M. and Kastensmidt, F. L.. Computer Efficient Modeling of SRAM Cell Sensitivity to SEU. In: Proceedings of the 6th IEEE Latin America Test Workshop, 2005. pp. 51--5.
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