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Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic
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Proceedings of the 18th annual symposium on Integrated circuits and system design table of contents
Florianolpolis, Brazil
SESSION: Test table of contents
Pages: 62 - 67  
Year of Publication: 2005
ISBN:1-59593-174-0
Authors
Egas Henes Neto  Universidade Estadual do Rio Grande do Sul, Brazil
Ivandro Ribeiro  Universidade Estadual do Rio Grande do Sul, Brazil
Michele Vieira  Universidade Estadual do Rio Grande do Sul, Brazil
Gilson Wirth  Universidade Estadual do Rio Grande do Sul, Brazil
Fernanda Lima Kastensmidt  Universidade Federal do Rio Grande do Sul, Brazil
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper, we propose a new approach for using Built-in Current Sensor (BICS) to detect not only transient upsets in sequential logic but also in combinational circuits. In this approach, the BICS is connected in the design bulk to increase its sensitivity to detect any current discrepancy that may occur during a charged particle strike. In addition, the proposed BICS can inform if the upset has occurred in the PMOS or NMOS transistors, which can generate a more precise evaluation of the corrupted region. The proposed approach was validated by Spice simulation. The BICS and the case-studied circuits were designed in the 100nm CMOS technology. The bulk BIC sensor detects various shapes of current pulses generated due to charged particle strike. Results show that the proposed bulk BICS presents minor penalties for the design in terms of area, performance and power consumption and it has high detection sensitivity.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Dodd, P. E. and Massengill, L. W. Basic Mechanism and Modeling of Single-Event Upset in Digital Microelectronics. IEEE Trans. Nucl. Sci., vol. 50, pp. 583--602, June 2003.
 
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Vargas, F. and Nicolaidis, M. SEU-Tolerant SRAM Design based on Current Monitoring. Fault-Tolerant Computing, 1994. FTCS-24. Digest of Papers., pages 106--115.
 
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Wirth, G., Vieira, M. and Kastensmidt, F. L.. Computer Efficient Modeling of SRAM Cell Sensitivity to SEU. In: Proceedings of the 6th IEEE Latin America Test Workshop, 2005. pp. 51--5.


Collaborative Colleagues:
Egas Henes Neto: colleagues
Ivandro Ribeiro: colleagues
Michele Vieira: colleagues
Gilson Wirth: colleagues
Fernanda Lima Kastensmidt: colleagues