Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers

ABSTRACT

Asynchronous controllers are very efficient to operate as high performance interfaces in heterogeneous synchronous/ asynchronous systems. Asynchronous controllers may be designed to operate either in the generalized fundamental mode (GFM) or in the input-output (I/O) mode. The latter are more robust to temperature variation and technology migration and may operate in faster environments. However, none of the existing synthesis tools, targeting circuits that operate in the I/O mode accept non-monotonic level sensitive signals (usually adopted to describe conditions in heterogeneous systems). Another limitation of these synthesis tools concerns the number of signals that may be present in the initial specification. This limitation comes from the input description that must be either a signal transition graph (STG) or a state graph (SG). In this article we present Miriã-SI, an extension of the Miriã-GFM synthesis tool that can synthesize such circuits. It starts from a state transition description known as multi-burst graph that is able to accept up to 200 signals. Non-monotonic signals are nicely handled. The resulting controllers, implemented in the feedback set-dominant latch architecture are guaranteed to be hazard free.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Automatic synthesis

General Terms:
Algorithms, Design, Performance

Keywords:
asynchronous logic, automatic synthesis, burst-mode, hazard, speed-independent