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Deterministic approaches to analog performance space exploration (PSE)
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 42nd annual Design Automation Conference table of contents
Anaheim, California, USA
SESSION: Special session: hierarchical design and design space exploration of analog integrated circuits table of contents
Pages: 869 - 874  
Year of Publication: 2005
ISBN:1-59593-058-2
Authors
Daniel Mueller  Techn. Univ. Muenchen, Munich, Germany
Guido Stehr  Techn. Univ. Muenchen, Munich, Germany
Helmut Graeb  Techn. Univ. Muenchen, Munich, Germany
Ulf Schlichtmann  Techn. Univ. Muenchen, Munich, Germany
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Performance space exploration (PSE) determines the range of feasible performance values of a circuit block for a given topology and technology. In this paper, we present two deterministic approaches for PSE. One approximates the feasible performance space based on linearized circuit models and is suitable for investigating a large number of performances. The other one computes discretizations of the Pareto front of competing performances. In addition, a motivation and application of PSE using a hierarchical design example is presented.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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www.muneda.com


Collaborative Colleagues:
Daniel Mueller: colleagues
Guido Stehr: colleagues
Helmut Graeb: colleagues
Ulf Schlichtmann: colleagues