Variation-tolerant circuits: circuit solutions and techniques

ABSTRACT

Die-to-die and within-die variations impact the frequency and power of fabricated dies, affecting functionality, performance, and revenue. Variation-tolerant circuits and post-silicon tuning techniques are important for minimizing the impacts of these variations. This paper describes several circuit techniques that can be employed to ensure efficient circuit operation in the presence of ever-increasing variations.

REFERENCES

• 1: Shekhar Borkar , Tanay Karnik , Vivek De, Design and reliability challenges in nanometer technologies, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996588]
• 2: Shekhar Borkar , Tanay Karnik , Siva Narendra , Jim Tschanz , Ali Keshavarzi , Vivek De, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775920]
• 3: K. A. Bowman et. al., "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale Integration," IEEE J. Solid-State Circuits, pp. 183--190, Feb. 2002.
• 4: J. Tschanz et. al., "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage", IEEE J. Solid-State Circuits, pp. 1396--1402, Nov. 2002.
• 5: J. Tschanz et. al., "Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors," IEEE J. Solid-State Circuits, pp. 826--829, May 2003.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design, Performance, Reliability

Keywords:
body bias, high-performance design, parameter variation