Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction

ABSTRACT

To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in the Vdd-programmable method consume a large amount of leakage. In this paper, we develop chip-level dual-Vdd assignment algorithms to guarantee that no low-Vdd interconnect switch drives high-Vdd interconnect switches. This removes the need of Vdd-level converters and reduces interconnect leakage and interconnect device area by 91.78% and 25.48%, respectively. The assignment algorithms include power sensitivity based heuristics with implicit time slack allocation and a linear programming (LP) based method with explicit time slack allocation. Both first allocate time slack to interconnects with higher transition density and assign low-Vdd to them for more power reduction. Compared to the aforementioned Vdd-programmable method using Vdd-level converters, the LP based algorithm reduces interconnect power by 65.13% without performance loss for the MCNC benchmark circuits. Compared to the LP based algorithm, the sensitivity based heuristics can obtain slightly smaller power reduction but run 4X faster.

REFERENCES

• 1: Kara K. W. Poon , Andy Yan , Steven J. E. Wilton, A Flexible Power Model for FPGAs, Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications, p.312-321, September 02-04, 2002
• 2: Fei Li , Deming Chen , Lei He , Jason Cong, Architecture evaluation for power-efficient FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA [doi>10.1145/611817.611844]
• 3: Jason H. Anderson , Farid N. Najm , Tim Tuan, Active leakage power optimization for FPGAs, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA [doi>10.1145/968280.968287]
• 4: Julien Lamoureux , Steven J. E. Wilton, On the Interaction Between Power-Aware FPGA CAD Algorithms, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.701, November 09-13, 2003 [doi>10.1109/ICCAD.2003.106]
• 5: A. Gayasen , Y. Tsai , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , T. Tuan, Reducing leakage energy in FPGAs using region-constrained placement, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA [doi>10.1145/968280.968289]
• 6: Fei Li , Yan Lin , Lei He , Jason Cong, Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA [doi>10.1145/968280.968288]
• 7: Fei Li , Yan Lin , Lei He, FPGA power reduction using configurable dual-Vdd, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996767]
• 8: Fei Li , Yan Lin , Lei He, Vdd programmability to reduce FPGA interconnect power, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.760-765, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382678]
• 9: J. H. Anderson , F. N. Najm, Low-power programmable routing circuitry for FPGAs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.602-609, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382647]
• 10: Yan Lin , Fei Li , Lei He, Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA [doi>10.1145/1046192.1046218]
• 11: Y. Lin and L. He, "Leakage efficient chip-level dual-vdd assignment with time slack allocation for FPGA power reduction," Tech. Rep. 05-257, UCLA Engr., available at http://eda.ee.ucla.edu
• 12: Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
• 13: M Berkelaar, lp-solver 3.2: a public domain (MI)LP solver. ftp://ftp.ics.ele.tue.nl/pub/lp solve/.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Algorithms, Design

Keywords:
FPGA, low power, programmable-Vdd, time slack