Simulation models for side-channel information leaks

ABSTRACT

Small, embedded integrated circuits (ICs) such as smart cards are vulnerable to so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power consumption, execution time, electromagnetic radiation and other information that is leaked by the switching behavior of digital CMOS gates. Ever since power attacks have been introduced in 1999, many countermeasures have been proposed. Often a significant increase in security has been touted. We will show that in order to assess the effectiveness of a countermeasure, a correct simulation model of the side-channel information leaks is vital. We will show that seemingly correct approximations can lead to completely flawed results.

REFERENCES

• 1: M. Renaudin , F. Bouesse , Ph. Proust , J. P. Tual , L. Sourgen , F. Germain, High Security Smartcards, Proceedings of the conference on Design, automation and test in Europe, p.10228, February 16-20, 2004
• 2: P. Kocher, R. Lee, G. McGraw, A. Raghunathan, and S. Ravi, "Security as a New Dimension in Embedded System Design", DAC, pp.735--760, June 2004.
• 3: A. Shamir, and E. Tromer, "Acoustic cryptanalysis", http://www.wisdom.weizmann.ac.il/~tromer/acoustic/, 2004.
• 4: B. Schneier, "A Hardware DES Cracker", Crypto-Gram Newsletter, http://www.schneier.com/crypto-gram-9808.html#descracker, August 1998.
• 5: K. Tiri , D. Hwang , A. Hodjat , B. Lai , S. Yang , P. Schaumont , I. Verbauwhede, A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA [doi>10.1145/1065579.1065639]
• 6: Paul C. Kocher , Joshua Jaffe , Benjamin Jun, Differential Power Analysis, Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology, p.388-397, August 15-19, 1999
• 7: Thomas S. Messerges , Ezzat A. Dabbish , Robert H. Sloan, Examining Smart-Card Security under the Threat of Power Analysis Attacks, IEEE Transactions on Computers, v.51 n.5, p.541-552, May 2002 [doi>10.1109/TC.2002.1004593]
• 8: Christophe Clavier , Jean-Sébastien Coron , Nora Dabbous, Differential Power Analysis in the Presence of Hardware Countermeasures, Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems, p.252-263, August 17-18, 2000
• 9: Adi Shamir, Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies, Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems, p.71-77, August 17-18, 2000
• 10: N. Pramstaller, F. Gurkaynak, S. Hane, H. Kaeslin, N. Felber, and W. Fichtner, "Towards an AES Crypto-chip Resistant to Differential Power Analysis", ESSCIRC, pp. 307--310, September 2004.
• 11: E. Oswald, S. Mangard and N. Pramstaller, "Secure and Efficient Masking of AES - A Mission Impossible?", Report 2004/134 in IACR Cryptology ePrint Archive, June 2004
• 12: S. Mangard, T. Popp, and B. Gammel, "Side-Channel Leakage of Masked CMOS Gates", CT-RSA, Feb. 2005.
• 13: K. Tiri, and I. Verbauwhede, "Place and Route for Secure Standard Cell Design", CARDIS, pp. 143--158, August 2004.
• 14: Luca Benini , Alberto Macii , Enrico Macii , Elvira Omerbegovic , Fabrizio Pro , Massimo Poncino, Energy-aware design techniques for differential power analysis protection, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775845]
• 15: H. Saputra , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , R. Brooks , S. Kim , W. Zhang, Masking the Energy Behavior of DES Encryption, Proceedings of the conference on Design, Automation and Test in Europe, p.10084, March 03-07, 2003
• 16: Catherine H. Gebotys, Design of secure cryptography against the threat of power-attacks in DSP-embedded processors, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.1, p.92-113, February 2004 [doi>10.1145/972627.972632]
• 17: Jean-Sébastien Coron , Paul C. Kocher , David Naccache, Statistics and Secret Leakage, Proceedings of the 4th International Conference on Financial Cryptography, p.157-173, February 20-24, 2000
• 18: Jean-Sébastien Coron, Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems, Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems, p.292-302, August 12-13, 1999
• 19: Kris Tiri , Ingrid Verbauwhede, A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation, Proceedings of the conference on Design, automation and test in Europe, p.10246, February 16-20, 2004
• 20: S. Mangard, "Hardware Countermeasures Against DPA - A Statistical Analysis of Their Effectiveness", CT-RSA, LNCS 2964, pp. 222--235, February 2004.
• 21: F. Mace, F. Standaert, I. Hassoune, J. Legat and J. Quisquater, "A Dynamic Current Mode Logic to Counteract Power Analysis Attacks", DCIS, November 2004

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
  B.7 INTEGRATED CIRCUITS

  E. Data
  E.3 DATA ENCRYPTION

General Terms:
Design, Security, Verification

Keywords:
countermeasure, differential power analysis, encryption, security IC, side-channel attack, simulation model, smart card