Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs

ABSTRACT

Application-Specific Block-Enabled (ASBE) SRAMs represent a viable solution for reducing energy consumption in embedded memories. The basic idea behind ASBE architectures is that of partitioning the memory array into a number of non-uniformly sized blocks, such that memory access cost is reduced. The number and sizes of the partitions yielding a minimum power implementation of the SRAM macro is determined by the partitioning algorithm based on the memory access profile obtained as a result of the application (or application mix) executed by the processor. Given the complexity of the design space we are dealing with, there are several degrees of freedom that the partitioning engine may exploit to come up with the most energy-efficient memory architecture. In this paper, we investigate how the quality of the partitioned memory depends on the architectural parameters that define the memory structure (e.g., min and max number of lines per partition, min and max number of words per line, granularity of the partitions); such parameters, in turn, are constrained by the technology and process of choice. We believe that the results presented in this work will provide very useful guidelines for a succesfull adoption of the ASBE approach in practice, as this design paradigm is gaining a lot of attention for the new generations of embedded systems.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.1 Semiconductor Memories
          Subjects: Static memory (SRAM)

General Terms:
Experimentation, Performance

Keywords:
DBL, DWL, SRAM, application-specific, embedded, memories, partitioning