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A sensitivity analysis of low-power repeater insertion
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 15th ACM Great Lakes symposium on VLSI table of contents
Chicago, Illinois, USA
SESSION: High-level low power design I table of contents
Pages: 244 - 247  
Year of Publication: 2005
ISBN:1-59593-057-4
Authors
Yuantao Peng  North Carolina State University, Raleigh, NC
Xun Liu  North Carolina State University, Raleigh, NC
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper, we perform the first quantitative study on the sensitivities of repeater power to available repeater width and candidate location, two key parameters of the dynamic programming (DP) based repeater insertion algorithms. Based on our analysis, we propose a simple yet effective scheme to select repeater widths and locations for DP-based algorithms, achieving an excellent trade-off between the solution quality and runtime. Experimental results have shown that, when combined with our sensitivity-guided scheme, the DP algorithm can attain more than 6 times speedup with negligible power degradation.


REFERENCES

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