Diagnosing multiple transition faults in the absence of timing information

ABSTRACT

As timing requirements in today's advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such algorithms capable of diagnosing multiple delay faults. One method uses multiple transition fault models and the other reasons with ternary logic values, thus achieving model independent diagnosis. Experiments are conducted on IS-CAS'85 combinational and full-scan version of ISCAS'89 se-quential circuits corrupted with multiple transition faults. The performance of both algorithms are evaluated and compared. The results show good efficiency and diagnostic resolution.

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INDEX TERMS

Primary Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Algorithms, Performance, Verification

Keywords:
delay faults, diagnosis, incremental, multiple faults, transition faults