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Interconnect capacitance extraction for system LCD circuits
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 15th ACM Great Lakes symposium on VLSI table of contents
Chicago, Illinois, USA
POSTER SESSION: Poster session 1 table of contents
Pages: 160 - 163  
Year of Publication: 2005
ISBN:1-59593-057-4
Authors
Yoshihiro Uchida  Osaka University, Osaka, Japan
Sadahiro Tani  SHARP Corporation
Masanori Hashimoto  Osaka University, Osaka, Japan
Shuji Tsukiyama  Chuo University
Isao Shirakawa  University of Hyogo
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

This paper discusses interconnect capacitance extraction for system LCD circuits, where coupling capacitance is much significant since a ground plane locates far away unlike LSI interconnects. We focus on a pattern matching method with interpolation to implement an accurate and efficient capacitance extraction system, and present good implementations that are suitable for system LCD circuits. To reduce computational cost, interconnect structures are spatially divided into several sub-regions considering capacitance coupling range, and analyzed in each sub-region using a capacitance database pre-characterized by a 3-D field solver. This paper evaluates tradeoff curves between characterization cost and extraction accuracy for four division methods in lattice structures that are basic and common structures in LCD driver circuits. Experimental results reveal efficient division methods for accurate capacitance extraction.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
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Collaborative Colleagues:
Yoshihiro Uchida: colleagues
Sadahiro Tani: colleagues
Masanori Hashimoto: colleagues
Shuji Tsukiyama: colleagues
Isao Shirakawa: colleagues