Effects of on-chip inductance on power distribution grid

ABSTRACT

With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We perform a case study work that evaluates relation between decoupling capacitance position and noise suppression effect, and we reveal that placing decoupling capacitance close to current load is necessary for noise reduction. We experimentally show that impact of on-chip inductance becomes small when on-chip decoupling capacitance is well placed according to local power consumption. We also examine influences of grid pitch, wire area, and spacing between paired power and ground wires on power supply noise. Minification of grid pitch is more efficient than increase in wire area, and small spacing reduces power noise as we expected.

REFERENCES

• 1: A. V. Mezhiba and E. G. Friedman, "Power Distribution Networks in High Speed Integrated Circuits," Kluwer Academic Publishers, 2004.
• 2: Y.-M. Lee and C. C.-P. Chen, "Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method," IEEE Transactions on Computer-Aided Design, Vol. 21, No. 11, pp.1343--1352, Nov. 2002.
• 3: Woo Hyung Lee , Sanjay Pant , David Blaauw, Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids, Proceedings of the 5th International Symposium on Quality Electronic Design, p.131-136, March 22-24, 2004
• 4: C. W. Fok and D. L. Pulfrey, "Full-chip power-supply noise: the effect of on-chip power-rail inductance," International Journal of High Speed Electronics and Systems, vol. 12, no. 2, pp. 573--582, 2002.
• 5: Howard H. Chen , David D. Ling, Power supply noise analysis methodology for deep-submicron VLSI chip design, Proceedings of the 34th annual conference on Design automation, p.638-643, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266307]
• 6: Kaushik Gala , David Blaauw , Junfeng Wang , Vladimir Zolotov , Min Zhao, Inductance 101: analysis and design issues, Proceedings of the 38th conference on Design automation, p.329-334, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378501]
• 7: A. Kurokawa, K. Hachiya, K. Tokumasu and H. Masuda, "Fast on-chip inductance extraction of VLSI including angled interconnects," IEICE Trans. Fundamentals, vol. E86-A, No. 4, pp. 841--845, Apr. 2003.
• 8: A. E. Ruehli, "Equivalent Circuit Models for Three-Dimensional Multiconductor Systems," IEEE Trans. MTT, Vol. MTT-22, No. 3, pp. 216--221, Mar 1974.
• 9: L. Smith, "Decoupling capacitor calculations for CMOS circuits," in Proc. IEEE 3rd Topical Meeting of Electrical Performance of Electronic Packaging, pp. 101--105, Nov. 1994.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Performance

Keywords:
decoupling capacitance, on-chip inductance, power distribution network, power supply noise