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Scheduling and dispatching: some issues of the critical ratio dispatch rule in semiconductor manufacturing
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Source Winter Simulation Conference archive
Proceedings of the 34th conference on Winter simulation: exploring new frontiers table of contents
San Diego, California
SESSION: Semiconductor manufacturing table of contents
Pages: 1401 - 1405  
Year of Publication: 2002
ISBN:0-7803-7615-3
Author
Oliver Rose  University of Würzburg, Würzburg, Germany
Sponsors
IEEE/CS : Institute of Electrical and Electronics Engineers/Computer Society
ASA : American Statistical Association
IEEE/SMCS : Institute of Electrical and Electronics Engineers/Systems, Man, and Cybernetics Society
INFORMS/CS : Institute for Operations Research and the Management Sciences/College on Simulation
NIST : National Institute of Standards and Technology
ACM: Association for Computing Machinery
(SCS) : The Society for Modeling and Simulation International
SIGSIM: ACM Special Interest Group on Simulation and Modeling
IIE : Institute of Industrial Engineers
Publisher
Winter Simulation Conference 
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ABSTRACT

In this paper, we examine the cycle time and on-time delivery performance of a semiconductor wafer fabrication facility (wafer fab) under critical ratio (CR) dispatch regime. It turns out that determining appropriate due dates for this rule is a critical task. We provide a detailed analysis of the wafer fab behavior for a large range of due date values. From the results of the experiments we develop a heuristic for conservative due date estimates.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Atherton, L. and R. Atherton. 1995. Wafer Fabrication: Factory Performance and Analysis. Boston: Kluwer.
 
2
Fowler, J. and J. Robinson. 1995. Measurement and improvement of manufacturing capacities (MIMAC): Final report. Technical Report 95062861A-TR, SEMATECH, Austin, TX.
 
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Wein, L. M. 1988. Scheduling semiconductor wafer fabrication. IEEE Transactions on Semiconductor Manufacturing, 1(3):115--130.