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Scheduling and dispatching: a simulation study on release, synchronization, and dispatching in MEMS fabrication
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Source Winter Simulation Conference archive
Proceedings of the 34th conference on Winter simulation: exploring new frontiers table of contents
San Diego, California
SESSION: Semiconductor manufacturing table of contents
Pages: 1392 - 1400  
Year of Publication: 2002
ISBN:0-7803-7615-3
Authors
Lixin Wang  Gintic Institute of Manufacturing Technology, Singapore
Loo Hay Lee  National University of Singapore, Singapore
Sponsors
IEEE/CS : Institute of Electrical and Electronics Engineers/Computer Society
ASA : American Statistical Association
IEEE/SMCS : Institute of Electrical and Electronics Engineers/Systems, Man, and Cybernetics Society
INFORMS/CS : Institute for Operations Research and the Management Sciences/College on Simulation
NIST : National Institute of Standards and Technology
ACM: Association for Computing Machinery
(SCS) : The Society for Modeling and Simulation International
SIGSIM: ACM Special Interest Group on Simulation and Modeling
IIE : Institute of Industrial Engineers
Publisher
Winter Simulation Conference 
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ABSTRACT

MEMS (microelectromechanical system) fabrication can be organized as three sub-processes, that is, the front-end process, the wafer cap process, and the back-end process. The coordination between the releases of raw wafers to the two parallel sub-processes, the front-end process, and the wafer cap process, is always an important issue. Previous research work has developed synchronization rules to create effective coordination. In this paper, new synchronization rules and dispatching rules are developed and they are evaluated with more release rules. From this much more extensive simulation experiment, it is found that there are significant two-factor and three-factor interactions among these three types of rules and we have to consider them all together in order to achieve the best performance for MEMS fabrication system. Moreover, the complicated relationship between the performances (cycle time and total work-in-process) is also indicated.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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