Low-power dual Vth pseudo dual Vdd domino circuits

ABSTRACT

Domino logic is a commonly used alternative to CMOS logic for designing circuits with high speed and/or low area requirements. Although it provides higher speed and lower area, domino logic has relatively higher dynamic power consumption than CMOS logic due to precharge/evaluate based operation. We propose a novel low-power domino gate design and also a methodology to use these low-power but slower gates with regular domino logic gates in combinational circuits to achieve low-power operation without changing the circuit delay. We apply our method on ISCAS'85 benchmark circuits and find that replacing the off-critical path normal domino gates with the proposed low-power gates reduces power consumption of the circuits by 20.6% on the average without affecting the circuit timing.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Optimization

General Terms:
Algorithms, Design, Performance

Keywords:
NMOS pull-up, domino logic, dual supply voltages, dual threshold voltages, low power