| A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35͘m CMOS technology |
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SBCCI
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Proceedings of the 17th symposium on Integrated circuits and system design
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Pernambuco, Brazil
SESSION: RF design
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Pages: 94 - 99
Year of Publication: 2004
ISBN:1-58113-947-0
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Downloads (6 Weeks): 2, Downloads (12 Months): 21, Citation Count: 0
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ABSTRACT
The design of a dual modulus prescaler 32/33 in a 0.35μm CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called Extended True Single Phase Clock (E-TSPC), an extension of the True Single Phase Clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Argüello. A.M.G. Estudo e Projeto de um sintetizador de freqüência para RF em tecnologia CMOS de 0,35͘m. Ms. Dissertation, Department of Eletronic Systems Engineering, University of São Paulo, São Paulo, Brazil, 2003 (in portuguese)
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Yuan, J.-R and Svensson. C. High speed CMOS circuit technique. IEEE J. Solid-State Circuits, 24, 1 (Feb 1989), 62--70.
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3
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Navarro, J. and Van Noije, W. E-TSPC: Extended True Single Phase Clock CMOS circuit technique for high speed applications. SBMICRO J. Solid-State Devices and Circuits, 5, 2 (1997), 21--26.
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4
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Navarro, J. Técnicas para projetos de ASICs CMOS de alta velocidade. PhD. Thesis, Department of Eletronic Systems Engineering, University of São Paulo, São Paulo, Brazil. 1998 (in portuguese).
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5
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Navarro, J. and Van Noije, W. A 1.6-GHz dual modulus prescaler using the Extended True-Single-Phase-Clock CMOS circuit tecnique (E-TSPC). IEEE J. Solid-State Circuits. 34, 1 (Jan. 1999), 97--102.
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7
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Chang, B., Park, J., and Kim, W. A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops. IEEE J. Solid-State Circuits, 31, 5 (May 1996), 749--752.
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Yang, C.-Y., Dehng, G.-K., Hsu, J.-M., and Liu, S.-I. New dynamic flip-flops for high-speed dual-modulus prescaler. IEEE J. Solid-State Circuits, 33, 10 (Oct. 1998), 1568--1571.
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9
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Yan, H, Biyani, M., O, K. K. A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2 latch and its application in a dual-modulus prescaler. IEEE J. Solid-State Circuits, 34, 10 (Oct. 1999), 1400--1404.
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Craninckx, J., and Steyaert. M.S.J. A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7 um CMOS. IEEE J. Solid-State Circuits, 31, 7 (July, 1996), 890--897.
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