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Modeling and designing high performance analog reconfigurable circuits
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Proceedings of the 17th symposium on Integrated circuits and system design table of contents
Pernambuco, Brazil
SESSION: Analog design table of contents
Pages: 49 - 54  
Year of Publication: 2004
ISBN:1-58113-947-0
Authors
Eric E. Fabris  UFRGS, Informatics Institute, Porto Alegre, Brazil
Luigi Carro  UFRGS, Informatics Institute, Porto Alegre, Brazil
Sergio Bampi  UFRGS, Informatics Institute, Porto Alegre, Brazil
Sponsor
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

The theoretical model for a mixed signal front-end interface for the SOC employing a fixed analog cell is presented in this work. The set of developed equations can be used for high level design space exploration. Moreover, the proposed architecture leads to programmable analog processing functions using digital modules, well suited to current FPGAs platforms and general purpose SOC. Some guidelines are addressed on how the proposed architecture can lead to greater level of analog design automation. Experimental results show constant performance over a large frequency range of the input signal, and validate the proposed design equations.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Fabris, E.E., Carro,L. and Bampi, S. An Analog Signal Inerface With Constant Performance for SOCs. In Proceedings of ISCAS 2003, Vol. 1, 773--776.
 
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Collaborative Colleagues:
Eric E. Fabris: colleagues
Luigi Carro: colleagues
Sergio Bampi: colleagues