PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems

ABSTRACT

Dynamically and Partially Reconfigurable Systems (DRSs) are those where any portion of the hardware behavior can be altered at application execution time. These systems have the potential to provide hardware with flexibility similar to that of software, while leading to better performance and smaller system size. However, the widespread acceptance of DRSs depends on adequate support to design and implement them. This work proposes a framework for DRS design and implementation named PADReH. The approach is compared to other propositions available in the literature. The first steps of the framework implementation are described, involving methods and tools to control the hardware reconfiguration process and the generation of partial bitstreams. The main contribution of the work is to provide means to systematically reduce the lack of support currently hampering the adoption of DRSs as a mainstream technology.

REFERENCES

• 1: Zhang, X., and Ng, K. W. A review of high-level synthesis for dynamically reconfigurable FPGAs. Microprocessors and Microsystems, v. 24, p.199--211. 2000.
• 2: Reinaldo A. Bergamaschi , William R. Lee, Designing systems-on-chip using cores, Proceedings of the 37th conference on Design automation, p.420-425, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337526]
• 3: DeHon, A. Comparing Computing Machines. In Proc. SPIE Configurable Computing: Technology and Applications. v. 3526, pp. 124--133, 1998.
• 4: Caspi, E., DeHon, A., and Wawrzynek, J. A streaming multithreaded model, In: Third Workshop on Media and Stream Processors, 2001.
• 5: Lehn, D., Hudson, R., and Athanas, P. Framework for architecture-independent run-time reconfigurable applications, In: SPIE Proceedings, November, 2000.
• 6: Martyn Edwards , Peter Green, Run-time support for dynamically reconfigurable computing systems, Journal of Systems Architecture: the EUROMICRO Journal, v.49 n.4-6, p.267-281, September 2003 [doi>10.1016/S1383-7621(03)00068-7]
• 7: Bapty, T., Neema, S., Scott, J., Sztipanovits, J., and Asaad, S. Model-integrated tools for the design of dynamically reconfigurable systems, Technical Report #ISIS-99-01, ISIS, Vanderbilt University, 2000.
• 8: Natarajan, S., Levine, B., Tan, C., Newport, D., and Bouldin, D. Automatic Mapping of Khoros-based Applications to Adaptive Computing Systems. In: MAPLD'99, pp. 101--107, 1999.
• 9: Michael Eisenring , Marco Platzner, A Framework for Run-time Reconfigurable Systems, The Journal of Supercomputing, v.21 n.2, p.145-159, February 2002 [doi>10.1023/A:1013627403946]
• 10: Ouaiss, I., Govindarajan, S., Srinivasan, V., Kaul, M., and Vemuri, R. An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. In: RAW'98, 1998.
• 11: Philip James-Roxby , Steven A. Guccione, Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations, Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, p.153, April 17-19, 2000
• 12: Xilinx, Inc. The JBits 3.0 SDK for Virtex-II. 2003. Available at http://www.xilinx.com/labs/downloads/ jbits/index.htm
• 13: Edson L. Horta , John W. Lockwood , Sérgio T. Kofuji, Using PARBIT to Implement Partial Run-Time Reconfigurable Systems, Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications, p.182-191, September 02-04, 2002
• 14: Anup Kumar Raghavan , Peter Sutton, JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs, Proceedings of the 16th International Parallel and Distributed Processing Symposium, p.192, April 15-19, 2002
• 15: Xilinx, Inc. Two Flows for Partial Reconfiguration: Module Based or Difference Based. Xilinx Application Note XAPP290, V1.1. 2003.
• 16: José Carlos Palma , Aline Vieira de Mello , Leandro Möller , Fernando Moraes , Ney Calazans, Core Communication Interface for FPGAs, Proceedings of the 15th symposium on Integrated circuits and systems design, p.183, September 09-14, 2002
• 17: Brião, E. Partial and Dynamic Reconfiguration for Intellectual Property Cores, MSc Dissertation, PUCRS-PPGCC-FACIN, Porto Alegre, Brazil, 2004. (In Portuguese)
• 18: Carvalho, E. RSCM: Configuration Control for Reconfigurable Hardware Systems, MSc Dissertation, PUCRS-PPGCC-FACIN, Porto Alegre, Brazil, 2004. (In Portuguese)
• 19: Moraes, F., and Calazans, N. R8 Processor Architecture and Organization Specification and Design Guidelines. 2003. Available at <http://www.inf.pucrs.br/~gaph/Projects/R8 /public/R8_arq_spec_eng.pdf>

INDEX TERMS

Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration); Algorithms implemented in hardware

General Terms:
Design, Experimentation, Theory

Keywords:
dynamically and partially reconfigurable systems, partial bitstream generation, reconfiguration control, run-time reconfiguration