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A simplified transmission-line based crosstalk noise model for on-chip RLC wiring
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2004 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Crosstalk noise analysis table of contents
Pages: 858 - 864  
Year of Publication: 2004
ISBN:0-7803-8175-0
Authors
Kanak Agarwal  University of Michigan
Dennis Sylvester  University of Michigan
David Blaauw  University of Michigan
Sponsors
IEICE : Institute of Electronics, Information and Communication Engineers
: IEEE Circuits and Systems Society
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 34,   Citation Count: 0
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ABSTRACT

In this paper, we present a new RLC crosstalk noise model that combines simplicity, accuracy, and generality. The new model is based on transmission line theory and is applicable to asymmetric driver and line configurations. The results show that the model captures both the waveform shape and peak noise accurately (average error in peak noise was 6.5%). A key feature of the new model is that its derivation and form enables physical insight into the dependency of total coupling noise on relevant physical design parameters. The model is applied to investigate the impact of various physical design optimizations (e.g., wire sizing and spacing, shield insertion) on total RLC coupled noise. Results indicate that common (capacitive) noise avoidance techniques can behave quite differently when both capacitive and inductive coupling are considered together.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Y. I. Ismail and E. G. Friedman, On-Chip Inductance in High Speed Integrated Circuits, Kluwer Acad. Publishers, 2001.
 
2
C. K. Cheng, J. Lillis, S. Lin and N. Chang, Interconnect Analysis and Synthesis, John Wiley & Sons, 2000.
 
3
A. Deutsch et al., "The Importance of Inductance and Inductive Coupling for On-Chip Wiring", Proc. Topical Meeting on Electrical Performance of Electrical Packaging, pp. 53--56, 1997.
 
4
D. Sylvester and K. Shephard, "Electrical Integrity Design and Verification for Digital and Mixed-Signal Systems on a Chip", Tutorial - Intl. Conf. Computer Aided Design, 2001.
5
 
6
L. He, N. Chang, S. Lin and O. S. Nakgawa, "An Efficient Inductance Modeling for On-Chip Interconnects", Proc. Custom Integrated Circuits Conference, pp. 457--460, 1999.
7
 
8
J. Davis and J. Meindl, "Compact Distributed RLC Interconnect Models -- Part II: Coupled Line Transient Expressions and Peak Crosstalk in Multilevel Networks", IEEE Trans. Electron Devices, pp. 2078--2087, Nov. 2000.
 
9
K. C. Gupta, Microstrip Lines and Slotlines, Boston Artech House, 1996.
 
10
H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, 1990.
 
11
B. Young, Digital Signal Integrity, Prentice Hall, 2001
Collaborative Colleagues:
Kanak Agarwal: colleagues
Dennis Sylvester: colleagues
David Blaauw: colleagues