A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement

ABSTRACT

This paper presents a methodology which can substantially reduce the bus power consumption in memory dominated systems. It systematically combines an activity driven placement of the memories and a bus segmentation approach for the interconnect to localize the wire switching activity and minimize the associated wire capacitive load of the memory bus. A factor of 2.8 in bus power reduction is achieved for a real life design while maintaining the same performance.

REFERENCES

• 1: International technology roadmap for semiconductors 2001 edition
• 2: P. R. Panda , F. Catthoor , N. D. Dutt , K. Danckaert , E. Brockmeyer , C. Kulkarni , A. Vandercappelle , P. G. Kjeldsberg, Data and memory optimization techniques for embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.149-206, April 2001 [doi>10.1145/375977.375978]
• 3: Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000 [doi>10.1145/335043.335044]
• 4: Yazdan Aghaghiri , Farzan Fallah , Massoud Pedram, Irredundant address bus encoding for low power, Proceedings of the 2001 international symposium on Low power electronics and design, p.182-187, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383128]
• 5: Hui Zhang , Jan Rabaey, Low-swing interconnect interface circuits, Proceedings of the 1998 international symposium on Low power electronics and design, p.161-166, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280876]
• 6: Benjamin Bishop , Victor Lyuboslavsky , N. Vijaykrishnan , Mary Jane Irwin, Design considerations for databus charge recovery, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.1, p.104-106, Feb. 2001 [doi>10.1109/92.920824]
• 7: A. Papanikolaou , M. Miranda , F. Catthoor , H. Corporaal , H. De Man , D. De Roest , M. Stucchi , Karen Maex, Global interconnect trade-off for technology over memory modules to application level: case study, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA [doi>10.1145/639929.639954]
• 8: J. Y. Chen , W. B. Jone , J. S. Wang , H.-I. Lu , T. F. Chen, Segmented bus design for low-power systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.1, p.25-29, March 1999 [doi>10.1109/92.748197]
• 9: Holt, G.; Tyagi, A.; "GEEP: a low power genetic algorithm layout system", IEEE 39th Midwest symposium on Circuits and Systems, 1996, Vol. 3, pp. 1337--1340
• 10: Yan Zhang, Wu Ye, Mary Jane Irwin, "An alternative architecture for on-chip global interconnect: segmented bus power modeling", Conference Record of the Thirty-Second Asilomar Conference on Signals, Systems& Computers, 1998, Vol. 2, pp. 1062--1065
• 11: W.-B. Jone , J. S. Wang , Hsueh-I Lu , I. P. Hsu , J.-Y. Chen, Design theory and implementation for low-power segmented bus systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.1, p.38-54, January 2003 [doi>10.1145/606603.606606]
• 12: Seceleanu, T.; Plosila, J.; Liljeberg, P.; "On-chip segmented bus: a self-timed approach", 15th Annual IEEE International ASIC/SOC Conference, 2002, pp. 216--220
• 13: M. Jimnez and M. Shanblatt, "Integrating a low-power objective into the placement of macro block-based Layouts", Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems, 2001, Vol. 1, pp. 62--65
• 14: F. Catthoor, K. Danckaert, C. Kulkarni, E. Brockmeyer, P. G. Kjeldsberg, T. Van Achteren, T. Omnes, "Data access and storage management for embedded programmable processors", ISBN 0-7923-7689-7, Kluwer Acad. Publ., Boston, 2002.
• 15: Radio broadcasting systems; digital audio broadcasting to mobile, portable and fixed receivers. Standard RE/JTC-00DAB-4, ETSI, ETS 300 401, May 1997.
• 16: http://www.imec.be/design/atomium/