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Test data compression technique using selective don't-care identification
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2004 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Effective test and diagnosis table of contents
Pages: 230 - 233  
Year of Publication: 2004
ISBN:0-7803-8175-0
Authors
Terumine Hayashi  Mie University, Japan
Haruna Yoshioka  Mie University, Japan
Tsuyoshi Shinogi  Mie University, Japan
Hidehiko Kita  Mie University, Japan
Haruhiko Takase  Mie University, Japan
Sponsors
IEICE : Institute of Electronics, Information and Communication Engineers
: IEEE Circuits and Systems Society
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
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ABSTRACT

In this paper, we propose an effective method for reducing test data volume under multiple scan chain designs. The proposed method is based on (1) reduction of distinct scan vectors (words) using selective don't-care identification, and (2) reduction of total test data volume using single/double length coding. In (1), don't-care identification is repeatedly applied under conditions that each bit in specified scan vectors is fixed to binary value (0 or 1). In (2), the code length for frequent scan vectors is shortened in the manner that the code length for rare scan vectors is designed as double of that for frequent ones. The proposed method achieves not only high compression efficiency, but also has a feature that the decompressor circuits are rather simple like combinational ones. The effectiveness of the proposed method is shown through experiments for ISCAS'89 and ITC'99 benchmark circuits


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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S. Kajihara, I. Pomeranz, K. Kinoshita and S. M. Reddy, "Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 12, pp. 1496--1504, 1995.
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T. Hayashi, Y. Morimoto, T. Shinogi, H. Kita and H. Takase, "X-Maximal Test Set Generation for Combinational Circuits," Proc. 3rd Workshop on RTL and High Level Testing, pp. 88--93, 2002.
 
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S. Davidson and Panelists, "ITC'99 Benchmark Circuits -- Preliminary Results," Proc. Int. Test Conf,. p. 1125, 1999. (http://www.cad.polito.it/tools/itc99.html)
Collaborative Colleagues:
Terumine Hayashi: colleagues
Haruna Yoshioka: colleagues
Tsuyoshi Shinogi: colleagues
Hidehiko Kita: colleagues
Haruhiko Takase: colleagues