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Low power design using dual threshold voltage
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2004 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Practical issues in logic synthesis table of contents
Pages: 205 - 208  
Year of Publication: 2004
ISBN:0-7803-8175-0
Authors
Yen-Te Ho  National Tsing Hua University HsinChu, Taiwan
Ting-Ting Hwang  National Tsing Hua University HsinChu, Taiwan
Sponsors
IEICE : Institute of Electronics, Information and Communication Engineers
: IEEE Circuits and Systems Society
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
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ABSTRACT

In this paper, we will study the reduction of static power consumption by dual threshold voltage assignment. Our goal is, under given timing constraint, to select a maximum number of gates working at high-Vth such that the total power gain is maximized. We propose an maximum independent set based slack assignment algorithm to select gates for high-Vth. The results show that our assignment algorithm can achieve about 68% improvement as compared to results without using dual Vth.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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S. Mutoh, et al., "1V Power Supply High-Speed Digital Circuits Technology with Multithreshold-voltage CMOS", IEEE Journal of Solid State Circuits, vol. 30, pp. 847--854, 1995.
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Collaborative Colleagues:
Yen-Te Ho: colleagues
Ting-Ting Hwang: colleagues